High dielectric capacitor and method of manufacturing the same

Details High dielectric capacitor and method of manufacturing the same High dielectric capacitor and method of manufacturing the same

2001-05-15

2003-06-17

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06579755

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a high dielectric capacitor. More particularly, the present invention relates to a high dielectric capacitor capable of preventing deterioration of dielectric property of a dielectric film generated during a subsequent thermal process.
2. Description of the Prior Art
Generally, as the degree of integration of a semiconductor device such as a DRAM is increased, the area a memory cell occupies in a semiconductor device or chip is rapidly reduced. For the operation of the memory device, however, capacitance of more than a certain amount per unit memory cell is necessarily secured. Therefore, there is a need for development of process technology by which the area occupied by a capacitor can be minimized while maintaining the capacitance necessary for the operation of the memory cell.
In order to secure a capacitance necessary for the operation of a semiconductor device in a limited area, the effective surface area of a storage electrode must be increased or a dielectric material having an improved dielectric property must be used.
Therefore, in compliance with these needs, a capacitor is manufactured using Ta
2
O
5
, BST (barium strontium titanate), or other suitable compounds in a manufacturing process of a device having a memory capacity more than four gigabytes (G). For reference, Ta
2
O
5
has more than five times the dielectric constant of a conventional dielectric made of an oxide film and a nitride film, and the dielectric constant of BST is higher than that of Ta
2
O
5
. The structure of the capacitor is formed as a MIS (metal insulator silicon) type made of, from top to bottom, a metal electrode, a dielectric, and a silicon electrode; or as a MIM (metal insulator metal) type made of, from top to bottom, a metal electrode, a dielectric, and a metal electrode.
If the lower electrode of the capacitor is formed of a metal instead of polysilicon, as in a MIS type, reduction in the capacitance due to formation of a depletion layer can be prevented. On the other hand, if the lower electrode is formed using polysilicon, as in a MIM type, a depletion layer is necessarily formed during operation of the semiconductor. The depletion layer acts as a capacitor serially connected to the capacitor, which is a component of a DRAM, thus reducing the total capacitance. If the lower electrode is formed of a metal, however, reduction in the capacitance as above is not generated since the thickness of the depletion layer is negligible.
Therefore, as the integration degree of a device is increased, a structure of a capacitor is such that only either an upper electrode or a lower electrode is formed of a metal or both the upper and lower electrodes are formed of metals.
A method of manufacturing a conventional capacitor having a MIM structure in which the upper and lower electrodes are formed of metals will be explained by reference to
FIGS. 1A
to
1
D.
FIG. 1A
shows a cross-sectional view of a semiconductor device in which after a first insulating film
3
is formed on a semiconductor substrate
1
in which a junction
2
is formed, the first insulating film
3
is applied in a pattern which exposes the junction
2
, forming a contact hole. A plug
4
is formed within the contact hole
2
a
by stacking polysilicon Ti/TiN
4
b
on top of
4
a
. The Ti/TiN
4
b
acts to reduce contact resistance with a metal electrode formed thereon and to prevent the polysilicon
4
a
and metal from diffusing.
FIG. 1B
shows a cross-sectional view of the semiconductor device in which, after an etching prevention layer
5
and an oxide film
6
are sequentially formed on the entire structure including the plug
4
, the oxide film
6
and the etching prevention layer
5
are sequentially patterned. The etching prevention layer
5
is formed by depositing a nitride film with thickness of several hundredths of an angstrom so that loss of the first insulating film
3
can be prevented upon etching the oxide film
6
.
FIG. 1C
shows a cross-sectional view of the semiconductor device in which, after a metal is deposited on the entire surface, the metal deposited on the oxide film
6
is removed for electrical separation between the memory cells, and a storage electrode
7
is formed at the patterned portion of the oxide film
6
and the etching prevention layer
5
so that it can contact the plug
4
. The metal deposited on the oxide film
6
is removed by an etch-back process or chemical mechanical polishing (CMP) process.
FIG. 1D
shows a cross-sectional view of the semiconductor device in which, after a dielectric film
8
and a plate electrode
9
are sequentially formed on the entire structure, a second insulating film
10
is formed on the plate electrode
9
so that the surface of the plate electrode
9
is essentially flat. The dielectric film
8
is formed of a high dielectric, e.g., Ta
2
O
5
or BST.
In case of adopting a COB (capacitor over bit line) structure, after the manufacture of the capacitor as above is completed, a metal wiring is formed. Then, in order to optimize the property of the MOS transistor, a thermal process is performed under a gas atmosphere in which hydrogen (H
2
) or hydrogen and nitrogen (N
2
) are mixed. In other words, as a word line, a bit line, a capacitor and a metal wiring are formed after the transistor is formed, during this process, the memory cell is degraded. Dangling bonds are therefore easily formed at the interface, which degrades the dielectric property of the transistor. If the thermal process is performed under a hydrogen gas atmosphere, so that hydrogen atoms can be diffused into the transistor located at the base portion, the dangling bonds are removed yielding a transistor having a desired property.
However, it has been reported that if the above thermal process is performed, the electrical property of the dielectric film is heavily degraded, generating a leakage current. The cause of this problem has yet to be clearly determined but it is thought that the cause are hydrogen atoms that penetrate into the dielectric film
8
during the thermal process, which causes a reduction reaction with the dielectric film since most dielectric films are made of oxide.
Current solutions to this problem include a technology in which a capping layer made of Al
2
O
5
is formed on the plate electrode (Ru) of a capacitor having a Ru/Ta
2
O
5
/Ru structure in order to prevent penetration of hydrogen ions. However, although penetration of hydrogen ions from the upper plate electrode is blocked, penetration of hydrogen ions from the bottom storage electrode is not blocked. Further problems exist when SiH
4
and NH
3
are used as a source gas when a nitride film, used as the etching prevention layer
5
, is deposited. If hydrogen ions remaining after deposition are not completely removed, the remaining hydrogen ions may penetrate into the dielectric film
8
.
SUMMARY OF THE INVENTION
A high dielectric capacitor in which a diffusion prevention film is formed at the side of a storage electrode and on a plate electrode to prevent penetration of hydrogen (H) ions during a subsequent thermal process, and a method of manufacturing the same are described.
In order to accomplish the above, a high dielectric capacitor has a storage electrode and a plate electrode, both made of metal or a metal oxide, and a high dielectric film formed between the electrodes. The dielectric film includes diffusion prevention films for preventing penetration of gas ions formed at the side of the storage electrode and on the plate electrode.
The high dielectric capacitor can be manufactured by the steps of: forming an insulating film on a semiconductor device in which a junction is formed so that the junction is exposed to form a contact hole
2
a
; forming a plug within the contact hole
2
a
; sequentially forming a first diffusion prevention film and an oxide film on the entire structure; sequentially patterning the oxide film, the first diffusion prevention film, and the etching prevention layer

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