Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-21
2000-01-04
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438222, 438296, 438301, H01L 218238, H01L 21336
Patent
active
060109289
ABSTRACT:
A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.
REFERENCES:
patent: 5055427 (1991-10-01), Haskell
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5289027 (1994-02-01), Terrill et al.
patent: 5627097 (1997-05-01), Venkatesan et al.
Hsu Chen-Chung
Lin Larry
Niebling John F.
Pompey Ron
United Microelectronics Corp.
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