Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-11
2003-05-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S532000, C257S535000
Reexamination Certificate
active
06559493
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for the creation of a Metal-to-Metal capacitor that provides increased capacitive values.
(2) Description of the Prior Art
Functions that are performed by semiconductor devices can generally be divided into functions of data manipulation or logic functions and functions of data storage. Functions of data manipulation are mostly related to digital data manipulation but can also comprise functions of analog data manipulation. Functions of data storage provide data retention capabilities that are performed by semiconductor memory devices. Two types of memory devices can be identified, that is memory functions that retain data in storage cells from which the data can only be read (Read Only Memories or ROM's) and memory functions whereby the data cannot only be read but can also be altered (Random Access Memories or RAM's).
The latter category of memory devices has been created using a number of different approaches, resulting in different types of RAM devices. Distinguished can be for instance the Dynamic RAM (DRAM), which uses capacitors as the storage medium and which are therefore, due to the non-permanent nature of the capacitive storage, periodically refreshed, and the Static RAM (SRAM) which depends on the presence of a power source for the retention of the stored data. DRAM memories offer advantages of economy of construction and of relatively high storage capabilities and have therefore attracted most of the attention in the semiconductor industry.
For the creation of analog integrated circuit devices and data retention or memory devices, capacitors are critical components. Capacitors can be divided in a number of different types of capacitors, dependent on and reflecting types of construction of the capacitor and the materials that are used in the construction of the capacitors. For instance, Metal Oxide Metal (MOM) capacitors are well known in the art and can be created at multiple levels in a semiconductor device and in contact with via openings. Other types of capacitors are referred to as, based on the materials that are used for the electrodes of the capacitors, polysilicon-silicon, polysilicon-polysilicon or metal-metal capacitors.
Is it required that the capacitor of a semiconductor device has a high storage retention, is further impervious to noise and does not require an excessive amount of surface area. To address these concerns, different constructs have been proposed for the creation of the capacitor of a DRAM cell. One such arrangement provides a stacked capacitor, which can be created as part of a DRAM cell. Another arrangement of a memory cell comprises a socalled cylindrical stacked type capacitor. With the stacked capacitor and the cylindrical capacitor, word lines and bit lines are provided to address and read out the level of voltage (data) that is stored in the capacitor.
Metal-metal capacitors are capacitors which have metal as the material of choice for the two electrodes of the capacitor, the metal of the two electrodes being separated by a dielectric. Metal-metal capacitors offer the advantage of providing a relatively constant value of capacitance over a relatively wide range of voltages that is applied to the plates of the capacitor. In addition, metal-metal capacitors have a relatively small parasitic resistance, reducing parasitic looses incurred by the metal-to-metal capacitor.
The creation of metal-to-metal capacitors is frequently and advantageously integrated with processing steps that are aimed at creating levels of interconnect metal in a semiconductor device. It is well known in the art that device miniaturization makes use of creating overlying layers of metal that are separated by layers of dielectric or insulation. The overlying layers of metal are patterned to form networks of interconnect lines, overlying patterns of interconnect lines are connected by creating openings or vias in the interposed layers of dielectric, these openings in turn are filled with a metal. For purposes of electrical performance, the thickness of the layer of dielectric that is interposed between adjacent and overlying layers of metal is limited to about 1 &mgr;m. In integrating the creation of a metal-to-metal capacitor with other processing steps of creating interconnect metal, the problem arises of creating adequate spacing between the plates of the capacitor since a typical thickness of the dielectric layer that is used for a metal-tometal capacitor is about 200 Angstrom. For this and other reasons, the typical processing sequence that is used for the creation of metal-to-metal capacitors is to first create a supporting level of dielectric over which a lower level of metal is created for the bottom plate of the capacitor. This lower level of dielectric may be surrounded by a protective barrier layer. The metal that is deposited for the lower electrode of the capacitor is polished, a first dielectric layer is deposited over the surface of the polished lower layer of metal in combination with forming interconnect lines on this level of metal. An opening that aligns with the lower electrode of the capacitor is etched in the first layer of dielectric. This first dielectric is removed from above the lower electrode of the capacitor after which a thin second layer of dielectric is deposited, filling the opening to form the dielectric of the capacitor. This second layer of dielectric (for the dielectric of the capacitor) is typically deposited to a thickness of between about 50 and 500 Angstrom. A third layer of dielectric is deposited over the second layer of dielectric, by creating an opening in this third layer of dielectric that aligns with the lower electrode of the capacitor, and by filling this opening with a metal, the second electrode of the capacitor is created. This creation of the second electrode of the capacitor can be combined with creating a network of interconnect lines that overlies the third layer of dielectric.
The latter highlighted process of creating a capacitor has a number of disadvantages. One of the main disadvantages of this process is that it allows only for the creation of planar capacitors, which are limited to a relatively low value of capacitance and therefore to a relatively low value of voltage storage capability. Also, for purposes of creating a capacitor, it is of importance to create a separating layer of dielectric between the two plates of the capacitor that has a uniform thickness. This requirement is difficult to meet for the creation of a planar capacitor because deposition thickness of the second, relatively thin layer of dielectric is difficult to control, especially so where silicon dioxide is used as a dielectric material of the capacitor in addition to using a barrier layer of titanium nitride (which is a frequently used barrier layer material) since titanium nitride chemically interacts with the silicon dioxide, compromising the integrity of the dielectric of the capacitor. Furthermore, the planar capacitor that is created in this manner extends over two levels of metallization of the semiconductor device while, in order to achieve a capacitance value of significance, the capacitor requires a relatively large surface area, which is undesirable in the era of sub-micron devices and device feature sizes.
The invention provides a method that allows for the creation of a stacked capacitor that provides a relatively large capacitive value over a relatively small surface area.
U.S. Pat. No. 6,100,155 (Hu) shows a MOM capacitor process.
U.S. Pat. No. 6,1509,183 (Fukuda et al.), U.S. Pat. No. 6,136,640 (Marty et al.) and U.S. Pat. No. 6,117,725 (Huang) show related capacitor patents.
U.S. Pat. No. 5,879,985 (Bambino et al.) shows a damascene process for a crown capacitor.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method for the creation of a stacked capacitor whereby a relatively large capacitive valu
Huang Chi-Feng
Lee Tzyh-Cheang
Lin Chih-Hsien
Wong Shyh-Chyi
Ackerman Stephen B.
Nelms David
Nguyen Dao H.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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