High density SRAM cell with latched vertical transistors

Details High density SRAM cell with latched vertical transistors High density SRAM cell with latched vertical transistors

2005-08-30

2005-08-30

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000

Reexamination Certificate

active

06936886

ABSTRACT:
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

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