High density semiconductor memory device (MBC cell)

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257309, 365149, H01L 2702

Patent

active

052742580

ABSTRACT:
A high-density semiconductor memory device and its manufacturing method are disclosed. The device has a plurality of memory cells, each consisting of one transistor and one capacitor on a substrate in a matrix form. The capacitor, in contact with the source region of the transistor, consists of a storage electrode having a hollow cylindrical electrode with a wall of predetermined thickness, and a column electrode surrounded by the cylindrical electrode. The capacitor further comprises a plurality of bars, a base plate electrode connecting the cylindrical and column electrodes to each other, a dielectric layer coating the whole surface of the storage electrode, and a plate electrode formed on top of the dielectric layer. According to this invention, a greater capacitance may be obtained while avoiding current leakage and the disparity of cell capacitance problems involved with a conventional stack-type capacitor having a ringed structure.

REFERENCES:
patent: 5047817 (1991-09-01), Wakamiya et al.
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5164337 (1992-11-01), Ogawa et al.
IBM Technical Disclosure Bulletin, "Stacked Capacitor Dram Cell with Vertical Fins (VF-STC)," vol. 33, No. 2, Jul. 1990.
Patetnt Abstracts of Japan, vol. 15, No. 308 (E-109) Aug. 1991, and JP-A-31 10 863 (NEC Corp.), May 10, 1991.
Patent Abstracts of Japan, vol. 14, No. 533 (E-1005) Nov. 22, 1990 and JP-A-22 26 761 (Hitachi Ltd.) Sep. 10, 1980.

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