Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2002-01-18
2004-05-11
Stoner, Kiley (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S215000, C257S737000, C438S613000
Reexamination Certificate
active
06732908
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to the field of microelectronics, and more particularly to the field of fabricating extremely small semiconductor devices and current, commonly referred to as “chips.”
RELATED INVENTIONS
The present invention is related to certain inventions assigned to the assignee of the present invention. These are in co-pending U.S. patent application Ser. Nos. 10/052,619 and 10/052,629.
BACKGROUND OF THE INVENTION
Increased levels of integration in the silicon transistor technology over the last two decades have facilitated the migration from large scale integrated (LSI) to very large scale integrated (VLSI) and now to ultra-large scale integrated (ULSI) circuits for use in silicon chips for computing, communication and micro controller applications. Optimum utilization of these highly integrated silicon chips requires a more space efficient packaging with supporting devices such as memory chips. Further, with the advent of mobile communication devices, hand held organizers and computing devices, there has also been a push to integrate such varied functions into a single compact system. This in turn has led to the push in the microelectronics industry towards system-on-a-chip (SOC) approach.
Simply stated, the SOC approach attempts to integrate as many of these different device functionalities on the same silicon chip so that a single large chip can provide a variety of functions to the end user. Although conceptually very attractive such an approach is practically daunting due to several reasons. First, the materials, fabrication processes and feature sizes optimum for the different microelectronic devices (such as memory chips, logic chips, wireless communication chips, etc.) are quite different from each other. Combining them all onto the same chip implies making compromises that can limit the performance achievable in each of the device blocks in the SOC. Second, integration of a large number of functional blocks requires a large chip size with many levels of wiring constructed on the chip. Both these factors tend to reduce the yield and increase the cost per chip, which is undesirable. Third, one has to design and build every unique combination of functions (e.g., memory and microprocessor, wireless communication and microprocessor, etc.) leading to a large variety of chip part numbers and product mix that is not conducive to cost reduced manufacture. Last, the expertise required for combining a diverse set of materials, process and integration schemes on a single SOC is often not available in a single enterprise as these are currently part of different microelectronic businesses.
An attractive alternative to SOC is system-on-a-package or SOP wherein a number of chips, each optimized for its unique function and perhaps manufactured in different factories specially tailored to produce the specific chips are combined on a first level packaging carrier that interconnects them and allows the resulting package to function as a single system. The level of interconnection and input-output- (I/O) density required in such a package is expected to be far greater than those currently available in printed circuit board or multilayer ceramic technologies. Since this SOP carrier with chips assembled on it is expected to replace an SOC, it is reasonable to expect that the interconnect and I/O densities should be somewhere between those used in the far back end of the line (FBEOL) interconnect levels on chips (typically wiring and vias on 500 nm to 1000 nm pitch) and the most aggressive packaging substrates (typically vias and wiring on 10,000 to 20,000 nm pitch). Extension of the FBEOL processes at the required wiring size and pitch for the SOP carrier is feasible if the carrier itself is made of silicon. In addition, however, the carrier would be required to support a high I/O density in order to interconnect the various device chips mounted on it. Greater the granularity of the system, that is, finer the division of the system into sub-units or chips, greater will be the number of I/Os required. It is expected that such I/O densities will necessitate bonding pads that are on the order of 5 to 10 &mgr;m size and spaces which are presently outside the realm of possibility of typical packaging I/O pads which are at least 10 to 20 times coarser in size and spacing.
It is therefore highly desirable to enable a microjoining structure to interconnect several chips on to a system-on-a-package carrier to achieve significantly higher input/output density between the chips as compared to the current state-of-the-art.
Accordingly, in order to overcome the inability of the prior art to produce a high-density array of I/O interconnects, it is the primary object of the present invention to provide a microjoint interconnect structure that will enable the use of chip processing techniques for the device chips and for the carrier such that the scheme will allow a very high density of interconnects, for example below 10 &mgr;m pitch, down to the very small 10-micron pitch, which is a much higher density than is possible with conventional chip to carrier joining.
SUMMARY OF THE INVENTION
In fulfillment of the above-stated objects, the present invention provides a microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.
The high density afforded by the use of chip processing methods and the controlled height of the studs enabled by a lithographic and chemical-mechanical polishing (CMP) process combination are unique to the invention. The carrier can be a silicon wafer, a ceramic substrate, or an organic chip carrier, although the silicon carrier is preferred since it allows the greatest microjoint density, low thermal expansion, and a high degree of planarity. The joining pads on the carrier are designed to be slightly larger than the stud structures and are provided with a recessed geometry so that the studs can slide into position and be contained within the carrier pads. Alternatively, the studs may be fabricated on the carrier and the recessed joining pads on the device chips.
The foregoing and still further objects and advantages of the present invention will be more apparent from the following detailed explanation of the preferred embodiments of the invention in connection with the accompanying drawing.
REFERENCES:
patent: 3458925 (1969-08-01), Napier et al.
patent: 3942245 (1976-03-01), Jackson et al.
patent: 4413308 (1983-11-01), Brown
patent: 5348214 (1994-09-01), Nishiguchi et al.
patent: 5668405 (1997-09-01), Yamashita
patent: 6020561 (2000-02-01), Ishida et al.
patent: 6107180 (2000-08-01), Munroe et al.
patent: 6153490 (2000-11-01), Xing et al.
patent: 6180881 (2001-01-01), Isaak
patent: 6285562 (2001-09-01), Zakel et al.
patent: 6339024 (2002-01-01), Petrarca et al.
patent: 6344125 (2002-02-01), Locke et al.
patent: 6358832 (2002-03-01), Edelstein et al.
patent: 6368484 (2002-04-01), Volant et al.
patent: 6476463 (2002-11-01), Kaneko et al.
patent: 6525275 (2003-02-01), Asai
patent: 6534863 (2003-03-01), Walker et al.
patent: 2002/0043466 (2002-04-01), Dordi et al.
patent: 2002/0111010 (2002-08-01), Walker et al.
patent: 2003/0049886 (2003-03-01), Salmon
patent: 2003/0092254 (2003-05-01), Walker et al.
patent: 2003/0122206 (2003-07-01), Bhattarai et al.
patent: 2003/0136813 (2003-07-01), Magerlein et al.
patent: 2003/0136814 (2003-07-01), Furman et al
patent: 2003/0137058 (2003-07-01), Magerlein et al.
patent: 019830159 (2000-01-01), None
patent: 363175450 (1988-07-01), None
Richard Volant, Kevin Petrarca, Peter Locke, James A. Tornello and Donald F. Canaperi, Tittle: “Replated Metal Structures for Semiconductor Devices”, U.S. patent application Ser. No. 09/657,
Furman Bruce Kenneth
Goma Sherif A.
Karecki Anna
Karecki Simon M.
Magerlein John Harold
Karecki Anna
Morris Daniel P.
Ohlandt Greeley Ruggiero & Perle L.L.P.
Stoner Kiley
LandOfFree
High density raised stud microjoining system and methods of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density raised stud microjoining system and methods of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density raised stud microjoining system and methods of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3255699