Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
438692, H01L 2100
A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.
patent: 5494854 (1996-02-01), Jain
Wang, Justin, "Advanced Techniquies for interlayer dielctric depostion and planarization", SPIE vol. 2090 Multilevel Interconnection (1993) pp. 85-92 .
Bowers, Jr. Charles
Liauh W. Wayne
Winbond Electronics Corp
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