High density mosfet fabrication method with integrated...

Details High density mosfet fabrication method with integrated... High density mosfet fabrication method with integrated...

1998-11-06

2001-03-06

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S179000, C438S286000

Reexamination Certificate

active

06197644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of integrated circuits, and more particularly, to the fabrication of insulated gate, field effect transistor (IGFET) devices.
2. Description of the Related Art
An insulated-gate field effect transistor (IGFET) device
5
, such as a metal-oxide semiconductor field-effect transistor (MOSFET) is shown in
FIG. 1. A
substrate
10
has a doped well region
12
, a p-doped well region that will be used for purposes of illustration. The substrate
10
has a p-doped channel region
14
that provides a conducting path between the n-doped source/drain region
16
A,
16
B and the n-doped source/drain region
18
A,
18
B. In addition, an p-doped punch-through region
20
is provided below the channel region
14
. Also formed in the substrate
10
are the isolation structures
22
and
24
. The gate structure of the IGFET device
5
includes a gate dielectric
26
, directly over the channel region
14
, and a gate electrode
28
over the gate dielectric
26
. The gate structure
26
,
28
can include spacers
30
,
32
formed against the walls of the gate structure
26
,
28
. An insulating layer
34
covers the substrate
10
and the gate structure
26
,
28
. The insulating layer
34
has vias formed therein, and the vias are filled with a conducting material. The conducting material provides conducting vias
36
to source/drain (electrode) regions
16
A,
16
B and
18
A and
18
B and to the gate electrode
28
. An insulating layer
38
, formed over insulating layer
34
, is patterned and the portions of the insulating layer formed by patterning are filled with conducting material to provide conducting paths
40
. The conducting paths
40
and the remaining insulating material
38
are referred to as the interconnect layer
38
,
40
, the interconnect layer providing the electrical coupling between the IGFET device
5
and the remainder of the integrated circuit.
The operation of the IGFET device
5
can be understood as follows. A voltage applied to the gate electrode
28
causes a transverse field in the channel region
14
. The transverse field controls (e.g., modulates) the current flow between source/drain region
16
A,
16
B and source/drain region
18
A,
18
B. The punch-through region
20
is formed to prevent parasitic effects that can occur when this region is not formed in the device
5
. The spacers
30
,
32
and the dual-structured, doped source/drain regions
16
A,
16
B and
18
A,
18
B address a problem generally referred to as the “hot-carrier” effect. When only one source/drain region
16
A and
18
A is present and is formed by a ion implantation aligned with the electrode structure
26
,
28
, charge carriers from these regions can migrate into the channel region
14
and be trapped by the gate dielectric
26
. These trapped charge carriers adversely effect the transverse electric field normally formed in the channel region
14
by a voltage applied to the gate electrode
28
. The problem is alleviated by lightly-doping source/drain regions
16
A and
18
A using a technique which aligns this doping procedure with the gate structure
26
,
28
. Spacers
30
and
32
are next formed on the walls of the gate structure
26
,
28
. Source/drain regions
16
B and
18
B are formed by an ion implantation, resulting in source/drain doping concentrations at normal levels, that aligns the source/drain regions
16
B and
18
B with the spacers
30
and
32
, respectively. (While this two-level doping procedure effectively eliminates the “hot-carrier” problem, the resistance between the two source/drain dual regions
16
A,
16
B and
18
A,
18
B is increased.) The isolation structures
22
,
24
provide electrical insulation between the device
5
and other areas of the integrated circuit.
In an effort to increase the density of components in an integrated circuit, the dimensions of the components have been increasingly reduced in scale. Many of the steps used in fabricating the components involve the use of masks that are patterned by optical techniques. For example, photoresist materials are used extensively. A layer of photoresist material is exposed to a pattern of (optical) radiation. The radiation changes the properties of the portions of the photoresist layer exposed to the radiation. Using these property changes, the photoresist layer can be processed to remove portions of the layer. The portions of the photoresist layer remaining after processing provide the pattern or mask for processing the integrated circuit. After years of continuously reducing the dimensions of the components of integrated circuits, limitations on optical resolution and on the registration of optical patterns are providing barriers for further reduction integrated circuit dimensions.
SUMMARY OF THE INVENTION
A need has therefore been felt for a technique for integrated circuit fabrication that has as a feature integrated circuit components having reduced dimensions compared to those available using current techniques. A further feature of the technique would be the fabrication of the reduced-dimension components without the use of masks requiring higher optical definition.
The aforementioned and other features are accomplished, according to the present invention, by using an etching process to reduce controllably the dimensions of a layer of material that has been patterned by an optical process. The material, with dimensions reduced by the etching process, then acts as a reduced-dimension mask for additional structure fabrication. Specifically, according to one embodiment of the present invention, a gate structure, provided with a layer of insulating material over the gate electrode, is formed with dimensions generally compatible with current optical technology. The insulating layer on the structure is then reduced by a controlled etching process. An oxide growth is then performed, the oxide growth covering the gate structure and the substrate. However, the insulating material has been selected such that the material does not participate in the oxide growth. The insulating material and the gate electrode are then anisotropically etched, the etching being stopped at the gate dielectric. As a result of this etching process, the original gate electrode has been separated into two gate electrodes. A source/drain implant is performed and spacers and conducting vias provided for coupling the device to an interconnect layer. The resulting structure includes two IGFET devices occupying roughly the area as a single device occupied previously. The fabrication of two IGFET devices was performed with a optical pattern resolution that previously provided only a single IGFET device.


REFERENCES:
patent: 4785337 (1988-11-01), Kenney
patent: 4954218 (1990-09-01), Okumura et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5541436 (1996-07-01), Kwong et al.
patent: 5633185 (1997-05-01), Yiu et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 6008081 (1999-12-01), Wu
S. Kusunoki et al, “Hot-Carrier-Resistant Structure by Re-Oxidized Nitrided Oxide Sidewall for Highly Reliable and High Performance LDD MOSFETS,”LSI Laboratory, Mitsubishi Electric Corporation, Japan, International Electron Devices Meeting, Washington, DC, Dec. 8-11, 1991 (5 pages).
Stanley Wolf, “Silicon Processing for the VSLI Era, vol. 3: The Submicron MOSFET,” Lattice Press, Sunset Beach, California, 1995 (26 pages).
Stanley Wolf, “Silicon Processing For The VSLI Era, vol. 2: Processing Integration,” Lattice Press, California, 1990, pp. 348-360, 436-440.

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