High density memory structure

Details High density memory structure High density memory structure

1998-01-14

2001-08-07

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S306000

Reexamination Certificate

active

06271556

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the invention is illustrated with regard to memory cell structures for a dynamic random access memory (DRAM) device, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as application specific integrated circuits (ASICs), microprocessors (MICROs), other memory devices, and the like.
In the fabrication of DRAM devices, memory storage capacity of each DRAM cell has long been a problem. In a DRAM cell, storage capacity is the greatest amount of electrical charge that can be stored in a dielectric material between a lower capacitor electrode and an upper capacitor electrode. This storage capacity is proportional to the surface area of the capacitor dielectric between these capacitor electrodes. Accordingly, a larger capacitor surface area corresponds to increased storage capacity.
Lower density DRAM cells used in 256 kbit DRAM designs relied upon planar capacitor structures, which were built roughly in the same horizontal spatial plane as the transistor gate electrodes. These capacitor structures were formed overlying transistor source/drain regions in the limited spatial region between the transistor gate electrode and the field oxide isolation region. These planar capacitor structures were effective in providing enough storage capacity for these lower density DRAM cells. As DRAM cell sizes became smaller for higher density devices, however, it was increasingly difficult to design a capacitor structure with enough storage capacity within this smaller cell size.
One technique used to improve memory storage capacity for these higher density DRAM cells is a stack capacitor. The stack capacitor forms its capacitor structure “over” the gate electrode of the field effect transistor, rather than being in the same spatial plane as the gate electrode. Therefore, the stack capacitor increases its capacitor surface area by fabrication of the capacitor structure over the gate electrode. A limitation with this capacitor type is, however, difficulty in processing. In fact, the stack capacitor creates a DRAM cell structure with an extremely complicated topography. This extremely complicated topography creates difficult fabrication techniques, rendering longer fabrication turn-around-times, lower device yields, and higher device costs.
Another technique proposed to improve memory storage capacity for higher density DRAM cells is a trench capacitor. The trench capacitor forms its structure within a recessed region or “trench” in the well region of the DRAM cell. This trench is defined by a selected width and depth. The trench also includes a trench side, defining the lower capacitor electrode. Overlying the trench side is the capacitor dielectric layer. A conductive fill material overlying this capacitor dielectric layer defines the upper capacitor electrode. Increased capacitor storage occurs with a greater capacitor surface area.
Greater capacitor surface area correlates to a trench design that is spatially deeper or wider. The trench width can not be substantially enlarged due to the limited amount of substrate surface area for each memory cell. Thus, the trench must be enlarged by fabrication of the deeper trench. This deeper trench, however, is often difficult to fabricate accurately due to its high aspect ratio. Another limitation is the possible presence of “soft error” problems due to the relatively large junction area associated with this trench design. A further limitation is sidewall doping used for the lower capacitor electrode often affects the quality of the capacitor dielectric layer.
From the above it is seen that a high density memory cell structure that is easy to fabricate, cost effective, and reliable is often desired.
SUMMARY OF THE INVENTION
The present invention provides a technique, including a method and structure, for an improved capacitor for a DRAM integrated circuit device. This improved capacitor is provided with a larger surface area without the formation of deeper trenches.
In a specific embodiment, the present invention provides a dynamic random access memory (DRAM) integrated circuit. This DRAM integrated circuit includes a semiconductor substrate comprising a recessed region. The recessed region has vertical sides extending from a bottom surface. A field effect transistor, including a source/drain region, is provided adjacent to the recessed region. The DRAM integrated circuit also includes an insulating layer overlying the recessed region. A lower capacitor plate overlying the insulating layer and over a portion of the field effect transistor is also provided. This lower capacitor plate is connected to the source/drain region. The DRAM integrated circuit further includes a capacitor dielectric overlying the lower capacitor plate, and an upper capacitor plate overlying the dielectric layer. The lower capacitor plate, capacitor dielectric, and upper capacitor plate define the capacitor structure.
In an alternative embodiment, a method of forming a capacitor structure for a dynamic random access memory integrated circuit element is provided. This method includes providing a semiconductor substrate, and forming a recessed region in the substrate. This recessed region has vertical sides extending from a bottom surface. The method also includes forming an insulating layer defined overlying the recessed region. A further step of forming a source/drain region adjacent to the recessed region is provided. The method includes forming a lower capacitor plate overlying the insulating layer and over a portion of the field effect transistor. This lower capacitor plate is connected to the source/drain region. The method also includes forming a capacitor dielectric overlying the lower capacitor plate, and forming an upper capacitor plate overlying the dielectric layer. The lower capacitor plate, capacitor dielectric, and upper capacitor plate define the capacitor structure.
A further alternative embodiment includes a bit-line structure for a dynamic random access memory integrated circuit. This bit-line structure includes a semiconductor substrate comprising a recessed region. This recessed region has vertical sides extending from a bottom surface. A field effect transistor is defined adjacent to the recessed region. An insulating layer is defined overlying the recessed region, and a conductor is defined within the recessed region. This conductor connects to the source/drain region, and defines a bit-line.
An alternative specific embodiment includes a method of forming a bit-line structure in a dynamic random access memory integrated circuit. This method includes providing a semiconductor substrate, and forming a recessed region in the semiconductor substrate. This recessed region has vertical sides extending from a bottom surface. The method also includes a step of forming an insulating layer defined overlying the recessed region, and forming a field effect transistor adjacent to the recessed region. A conductor is defined within the recessed region. This conductor connects to the source/drain region, and defines a bit-line.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.


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Wolf et al., “Chemical Vapor

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