High density integrated circuit process

Details High density integrated circuit process High density integrated circuit process

1997-04-23

1998-12-22

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438300, 438947, H01L 218234

Patent

active

058518835

ABSTRACT:
A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

REFERENCES:
patent: 5168072 (1992-12-01), Moslehi
patent: 5470776 (1995-11-01), Ryou
patent: 5670402 (1997-09-01), Sogawa et al.

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