High density floating gate flash memory and fabrication...

Details High density floating gate flash memory and fabrication... High density floating gate flash memory and fabrication...

2002-09-16

2003-12-09

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000

Reexamination Certificate

active

06660588

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a structure and a process for fabrication of a semiconductor device including a metal conductive element, in particular to a structure and process for fabrication of a floating gate in a flash memory device.
BACKGROUND ART
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions.
However, due to complex process technologies used in fabrication of state of the art flash memories, further improvement of memory density has become more challenging.
A floating gate flash memory device includes a floating gate electrode upon which electrical charge is stored. The floating gate electrode is formed on a tunnel oxide layer which overlies a channel region residing between the source and drain regions in a semiconductor substrate. The floating gate electrode together with the source and drain regions form an enhancement transistor. Typically, the floating gate electrode has been formed of polysilicon. Metal floating gates have also been used.
Referring to
FIG. 1
, there is schematically shown in cross-section a conventional floating gate flash memory device or cell
10
suitable for use in a floating gate flash EEPROM device. The cell
10
includes source/drain regions
12
and
14
located in a semiconductor substrate
16
. The source and drain regions
12
and
14
are separated by a channel region
18
. A “tunnel” or bottom dielectric material layer
20
overlies the source and drain regions
12
and
14
and the channel region
18
. A floating gate electrode
22
overlies the tunnel dielectric layer
20
. The floating gate electrode
22
may be polysilicon or polysilicon-germanium, a metal or a silicide, for example. The floating gate electrode
22
is separated from a control gate electrode
26
by an interlayer dielectric layer
24
. The control gate electrode
26
, the interlayer dielectric
24
and the floating gate electrode
22
form a floating gate flash memory cell structure, which may be referred to as a stack gate.
It should be noted that the floating-gate flash memory cell
10
is a symmetrical device. Therefore, the use of the terms “source” and “drain,” as they are commonly used with conventional transistor devices, may be confusing. For example, each floating gate flash memory cell
10
comprises a pair of adjacent source/drain regions
12
,
14
. During program, erase and read functions, one of these two source/drain regions
12
/
14
will serve as a source, while the other will serve as a drain. In conventional transistor terminology, electrons travel from the source to the drain. Which of the source/drain regions
12
/
14
functions as a source, and which of the source/drain regions
12
/
14
functions as a drain, depends on the function being performed and on the manner in which the floating gate
22
is being addressed (i.e., whether it is being programmed, erased or read). Thus, it is to be understood that references to source or drain may refer to different structures at different times.
In a floating gate flash memory device, electrons are transferred to the floating gate electrode
22
through the tunnel dielectric layer
20
overlying the channel region
18
of the floating gate flash memory cell
10
. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating gate electrode
22
by the overlying control gate electrode
26
. The control gate electrode
26
is capacitively coupled to the floating gate electrode
22
, such that a voltage applied on the control gate electrode
26
is coupled to the floating gate electrode
22
through the interlayer dielectric layer
24
, which may be referred to as the interpoly dielectric when both the floating gate and the control gate are formed of or comprise polysilicon. The floating gate flash memory device
10
is programmed by applying a high positive voltage to the control gate electrode
26
, and a lower positive voltage to the drain region
14
, which transfers electrons from the channel region
18
to the floating gate electrode
22
. Electron injection carries negative charge into the floating gate. This injection mechanism is normally induced by grounding the source region
12
and a bulk portion of the substrate
16
, applying a relatively high positive voltage to the control gate electrode
26
, for example, +12 Volts (V), to create an electron attracting field and applying a positive voltage of moderate magnitude (i.e., approximately +6 V to +9 V) to the drain region
14
in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates on the floating gate
22
, the negative potential of the floating gate
22
raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region
18
during a subsequent “read” mode. The magnitude of the read current is used to determine whether an EEPROM cell is programmed or not. Typically, in the read mode, a relatively low positive voltage, for example, +1.5 V, is applied to the drain region
14
, +5 V is applied to the control gate electrode
26
and 0 V is applied to the source region
12
of the floating gate flash memory cell
10
.
The act of discharging the floating gate
22
is called the erase function for a flash EEPROM cell. This erasure function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate
22
and the source region
12
of the transistor (source erase or negative gate erase) or between the floating gate
22
and the substrate
16
via the channel region
18
(channel erase). The “flash” EEPROM derives its name from the feature that all of the cells in a row can be erased at once.
One concern with floating gate flash memories is variation in Vt, the threshold voltage of the floating gate cell. For example, if the target Vt is 3 v, the range of actual Vt observed may be from 2.7 v to 3.3 v. This is undesirable, since such variation creates uncertainty as to the program state of the cell. Conventional floating gate cells use lightly doped polysilicon as the charge storage medium. If the doping is non-uniform, the non-uniformity can increase the range of Vt, and there may be a voltage drop across the floating gate if the doping level is too low. In addition, there is the problem of the depletion effect which may be observed in semiconductor materials such as polysilicon. Such problems may be avoided by use of a metal floating gate.
A second concern with floating gate flash memories is the work function of the floating gate material, and the energy barrier height which must be overcome by electrons during programming, reading and erasing floating gate cells.
A continuing concern in the industry is reduction of size and increase in density of components of semiconductor devices, and in particular, in flash memory devices. One way to increase higher density of programmable/erasable memory bits is to minimize the memory cell pitch. However, the present limits of lithography have been encountered in the drive towards ever-smaller and more dense

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