Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-08-20
2000-11-07
Smith, Matthew
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438259, 438212, 438268, 257315, 257319, H01L 213205, H01L 214763
Patent
active
061436364
ABSTRACT:
A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar. The control gates are formed together with interconnecting gate lines. First source/drain terminals are row addressable by interconnection lines disposed substantially orthogonal to the gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only 2F.sup.2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than 2F.sup.2 is needed per bit of data.
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Forbes Leonard
Noble Wendell P.
Keshavan Belur
Micro)n Technology, Inc.
Smith Matthew
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