Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-26
2003-02-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S393000, C438S397000, C438S250000, C438S254000, C438S669000, C438S738000
Reexamination Certificate
active
06514819
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an high capacity DRAM device having a smaller cell size as well as having a higher storage capacity. This process also relates to a process for preparing “memories” and other semiconductor devices with smaller dimensions and precise controls. In particular, this invention relates to a process for preparing DRAM's having a smaller cell size with high storage capacities and the cell layout of a high density DRAM product having a capacity as high as four gigabits.
BACKGROUND OF THE INVENTION
In recent years, in the area of semiconductor memory devices such as DRAM, 4M and 16M DRAMs have been mass-produced, and 64M DRAMs have been studied. In DRAMs, the typical three dimensional structures such as a trench type and a stack type have been developed. The trench type is manufactured in a groove provided on the semiconductor substrate, and the stack type is formed by laminating in three dimensions the conductive layers on the surface of the semiconductor substrate. The trench type has a flatter surface than the stack type, providing advantages for lithography but has serious operating disadvantages. The operation voltage is changed by leakage of current and punch-through between adjacent trenches. Electron-hole pairs generated by &agr;-particles transmitted inside the substrate are also a problem.
The stack type is formed by laminating element layers on the substrate, and the fabrication process sequence is simpler than for the trench type and does not have the operating deficits noted above. As a result, the stack type is more attractive than the trench type.
A limiting factor in the construction of stack type DRAMs in smaller cell sizes is the minimum storage capacity of 25 fF required for proper operation of a DRAM, that is, the cell capacity required per cell and the practical limit of photolithography techniques for achieving smaller dimensions. As the memory device is made to be more highly integrated and thus smaller in size, the area occupied by each cell is reduced, thus reducing the area available for each capacitor. To be functionally operable, the capacitor must have a large capacity, even as the size of the memory cell is reduced.
The chip size of a DRAM product is determined by the formula:
Chip Area=
AP+AM
Where:
AP is the Area of Peripheral circuits; and
AM is the Area of total Memory cells and is calculated by the formula:
AM=Total Bits (or density)×a Cell Area
Normally, AM occupies more than 55 percent of the total chip area in a high density DRAM. Because the smaller the chip size, the lower the production cost, every effort is directed to reducing the cell size. It can be shown that the memory cell size can be estimated by the formula:
Cell Area=2×(
AP+
2&dgr;)×
WP/AE
Wherein:
AP=Active Pitch;
&dgr;=Spacing of a bit line contact to the word line due to alignment limitations of photolithography (alignment errors);
WP=Word Line Pitch; and
AE=Area Efficiency.
In the produce and process of this invention, AE can be greater than previously known configurations, being above 80% and as high as about 100%.
Prior art approaches have focused on reducing the Cell Area by scaling but have reached limits in size reduction and tolerances due to the limits of photolithography, process techniques, and the need to make a capacitors having capacities greater than 25 fF. Similar constraints have limited the Area Efficiency for a typical 16 M DRAM to less than 80 percent.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a process for manufacturing a semiconductor device which provides component widths and spacings of in a range down to 1000 Å and smaller in horizontal planes by using the existing optical stepper or other advanced conventional lithographic exposure systems and even smaller dimensions in a range down to 700 Å using more advanced X-ray and more precise RIE techniques.
It is another object of this invention to provide a smaller DRAM cell structure which provides a theoretical efficiency of 100 percent.
It is a still further object of this invention to enable the construction of DRAMs having a density of up to four gigabits per device without sacrificing the cell capacity.
A further object of this invention is the provision of a DRAM having components which are entirely constructed in straight line structures, avoiding stress points, and yielding a more stable, low leakage product.
It is a still further object of this invention to provide a DRAM having word and active line arrays each of which are straight, have a uniform width, and have a uniform, minimum spacing from adjacent members of their respective arrays, the word and bit lines being in a configuration perpendicular to each other. In summary, one process of this invention is to produce a desired width of a product material in small dimensions in a range down to 800 Å. The process comprises the following steps:
a) depositing a form material on the surface of a product material;
b) removing a portion of the form material by vertical etching using photolithography to leave a sidewall of said form material;
c) depositing a layer of masking material over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material;
d) removing masking material by vertical RIE until the form material is exposed, leaving a predetermined width of masking material, and removing the form material until the underlying product material is exposed;
e) removing portions of the product material which are not protected by the masking material to leave a desired width of product material corresponding to the width of the masking material; and
f) removing the masking material, leaving a desired width of said product material.
The form material can be nitride, the masking material can be oxide, and the product material is a conductor such as doped polysilicon. Examples of suitable products formed by this process are word lines and capacitor plates.
Another process of this invention forms a small spacing d between widths of material. This can be useful for reducing spacings between capacitor plates, conductors or transistors, and in reducing the size of field oxide areas, for example. It can also yield products such as bit lines or word lines with reduced widths. The process for forming a desired space between adjacent portions of a product material having a width e comprises the following steps:
a) depositing a form material on the surface of a product material;
b) removing a center portion of the form material by vertical etching using photolithography to leave form materials having widths W with opposed sidewalls spaced apart by a distance D which is greater than the desired spacing d by 2&Dgr;;
c) depositing a layer of masking material over the form material and product material, the layer of masking material having a thickness correlating to &Dgr;;
d) removing masking material by vertical RIE until the form material is exposed, leaving &Dgr; widths of masking material contacting each of the opposed sidewalls of the form material;
e) removing form material by etching;
e) removing portions of the product material which are not protected by the masking material; and
f) removing the form material and the masking material, leaving adjacent pairs of adjacent widths of product material, each having a width e of in a range down to 800 Å, the desired spacing d between adjacent pairs of product material being in a range down to 700 Å; and a spacing W between adjacent widths of a product material.
In this process, each of the form material, masking material and product material is a member independently selected from the group consisting of nitride, oxide, conductor and laminate combinations thereof. Preferably, the form material and the masking material are not the same member, and the masking material and the product material are not the same member. For example, the for
Ace Memory, Inc.
Kennedy Jennifer M.
Niebling John F.
Townsend and Townsend / and Crew LLP
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