High capacitance damascene capacitors

Details High capacitance damascene capacitors High capacitance damascene capacitors

2001-08-17

2003-09-09

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S253000, C438S396000, C257S306000, C257S301000, C257S295000

Reexamination Certificate

active

06617208

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of semiconductor devices and fabrication and more specifically to high capacitance damascene capacitors.
BACKGROUND OF THE INVENTION
Capacitors built into the backend interconnect structures are useful in some circuits. Currently there are a number of schemes for fabricating such capacitors using aluminum based interconnect technology. Here, silicon dioxide is used to form the isolation layers between the various aluminum metal layers in the integrated circuit. With a dielectric constant of about 3.9 silicon dioxide is a suitable capacitor dielectric. Current schemes involve using the various metal levels as the plates of the capacitor structures. Such a capacitor is shown in FIG.
1
. In the Figure, silicon dioxide layers
12
,
14
,
16
,
18
, on the silicon substrate
10
represent the isolation layers between the various aluminum metal layers
22
. Alternate metal layers
22
are connected using vias
24
to increase the capacitance of the structure.
The requirement of higher clock rates has lead to the use of copper to form the metal interconnect lines in integrated circuits. In addition to the use of copper, isolation layers such as florosilicate glass (FSG) (dielectric constant ≈3.6) and organosilicate glass (OSG) (dielectric constant ≈2.6) are currently being used to take advantage of the lower dielectric constant of such materials compared to silicon dioxide. To achieve the same capacitance value using a dielectric with a lower dielectric constant, capacitors with larger areas have to be formed. This increased area requirement is in direct contrast to the requirement of higher integration and reduced area devices. In integrated circuits using copper interconnect lines, there is a need for a high capacitance structure with reduced area.
SUMMARY OF THE INVENTION
The present invention describes a high capacitance damascene capacitor and a method for making the same. The capacitor comprises: a first conductive layer with a top surface; a second conductive layer with a bottom surface; and a dielectric layer adjacent to said top surface of said first metal layer and to said bottom surface of said second metal layer.
In addition to the above described capacitor structure, the first conductive layer is copper, the second conductive layer is a material selected from the group consisting of aluminum, aluminum oxide, tantalum nitride, titanium nitride, tungsten, tungsten nitride, silicon carbide, and their alloys, and the dielectric layer is silicon nitride.
A method of making the high capacitance damascene capacitor according to the instant invention comprises: providing a silicon substrate with a first dielectric film containing at least one copper layer; forming a second dielectric layer over said first dielectric layer and said copper layer; forming a first conductive layer over said first dielectric layer; and removing a region of said first conductive layer such that a portion of said second dielectric layer remains between said first conductive layer and said copper layer. The above described method further comprises: forming copper contacts to said first conductive layer; and forming a second copper layer that electrically contacts said copper contacts. In addition to the above, the second dielectric layer is an etch-stop/barrier layer.


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