High breakdown voltage twin well device with source/drain region

Details High breakdown voltage twin well device with source/drain region High breakdown voltage twin well device with source/drain region

1999-02-19

2000-02-15

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257343, 257288, 257409, H01L 2976, H01L 2994, H01L 31062, H01L 31113, H01L 31119

Patent

active

060256281

ABSTRACT:
An FET semiconductor device comprises a doped silicon semiconductor substrate having a surface. The substrate being doped with a first type of dopant. An N-well is formed within the surface of the P-substrate. A P-well is formed within the N-well forming a twin well. Field oxide regions are formed on the surface of the substrate located above borders between the wells and regions of the substrate surrounding the wells. A gate electrode structure is formed over the P-well between the field oxide regions. A source region and a drain region are formed in the surface of the substrate. The source region and the drain region are self-aligned with the gate electrode structure with the source region and the drain region being spaced away from the field oxide regions by a gap of greater than or equal to about 0.7 .mu.m.

REFERENCES:
patent: 5072267 (1991-12-01), Hattori
patent: 5430324 (1995-07-01), Bencuya
patent: 5652458 (1997-07-01), Ahn
"VLSI Technology", McGraw Hill Book Company, N.Y., p129-131 (1988).

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