Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-02
2002-09-24
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06455386
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of semiconductor component manufacturing. More specifically, the present invention relates the manufacturing, in a semiconductor substrate of high and low voltage CMOS transistors, usable for example in memory devices.
2. Discussion of the Related Art
FIGS. 1
to
9
schematically illustrate, in cross-sectional view, successive steps of a method of manufacturing different high and low voltage MOS transistors on the same substrate according to a conventional method.
As illustrated in
FIG. 1
, a lightly-doped substrate
1
of a first conductivity type, for example P, on which lightly-doped wells
3
of opposite conductivity type N have been formed, is considered. It should be noted that “substrate” here is used to designate an upper layer or region of a semiconductor component, for example, an integrated circuit. Several insulated structures
2
formed of an insulating layer, for example, silicon oxide, and of a semiconductive layer, for example, polysilicon, meant to form the gates of each of the transistors, have also been formed on this substrate. A thicker gate oxide for high voltage transistors than for low voltage transistors may be provided.
It is desired to form, in substrate
1
, in the left-hand portion of the drawings, a high voltage N-channel transistor HTN and a low voltage N-channel transistor LTN. It is desired to form in well
3
, in the right-hand portion of the drawings, a high-voltage P-channel transistor HTP and a low voltage P-channel transistor LTP. In the following description, HTN, LTN, HTP or LTP will designate a completed transistor as well as a portion of the substrate or the well in which the corresponding transistor is being formed.
It is desired to form LDD-type transistors, among which, for high voltage transistors HTP and HTN, the heavily-doped drain/source contact region is more distant from the channel region than for low voltage transistors LTP and LTN.
At the next step, illustrated in
FIG. 2
, a first masking layer
4
is formed, to expose portions of the substrate in which transistors HTN and LTN are to be created. A low dose implantation of an N-type dopant adapted to forming lightly-doped drain and source regions
5
is performed. This implantation will be called hereafter LDD
N
implantation.
At the next step, illustrated in
FIG. 3
, a second masking layer
6
is formed, to expose N-type wells
3
in which transistors HTP and LTP are to be created. A low dose implantation of a P-type dopant adapted to forming lightly-doped drain and source regions
7
is performed. This implantation will be called hereafter. LDD
p
implantation.
At the next step, illustrated in
FIG. 4
, an insulating layer
8
, typically silicon oxide, is deposited over the entire structure (full plate).
At the next step, illustrated in
FIG. 5
, oxide layer
8
is etched without masking to only leave lateral spacers
9
on the edges of insulated gate structures
2
of the transistors.
At the next step, illustrated in
FIG. 6
, a third masking layer
10
is deposited. Third mask
10
is etched to completely cover P-channel transistor areas HTP and LTP, to completely expose low voltage transistor areas LTN, and to cover the gates of high voltage transistors HTN by laterally extending beyond these. A high dose N-type doping is then performed to make heavily-doped N-type drain/source contact regions
11
of transistors HTN and LTN. The pattern of mask
10
is such that regions
11
are more distant from the gates of high voltage transistors HTN than from the gates of low voltage transistors LTN. Indeed, for the latter, the distance between the projection of the gate and the contact regions is determined by spacers
9
. Further, the drain/source contact regions of two adjacent transistors are distinct from each other.
At the next step, illustrated in
FIG. 7
, drain/source contact regions
13
of transistors HTP and LTP are made similarly. For this purpose, a fourth masking layer
12
is deposited. Fourth mask
12
is etched to completely cover N-channel transistor areas HTN and LTN, to completely expose low voltage transistor areas LTP, and to cover the gates of high voltage transistors HTP by laterally extending beyond these. A high dose P-type doping is then performed to make heavily-doped P-type drain/source contact regions
13
of transistors HTP and LTP. The pattern of mask
12
is such that regions
13
are more distant from the gates of high voltage transistors HTP than from the gates of low voltage transistors LTP. Indeed, for the latter, the distance between the projection of the gate and the contact regions is determined by spacers
9
. Further, the drain/source contact regions of two adjacent transistors are distinct from each other.
At the next step, illustrated in
FIG. 8
, an insulator layer
14
, typically a multiple layer structure, for example, of titanium, titanium nitride, and silicon oxide is deposited over the full plate.
At the next step, illustrated in
FIG. 9
, layer
14
is opened above the drain/source contact regions of all transistors. Then, a metal silicide layer
15
, typically titanium silicide, is formed by high temperature fast thermal anneal on all apparent silicon surfaces. It should be noted that this silicidation is also performed on the gates of low voltage transistors LTN and LTP.
A disadvantage of this method is the etching of oxide layer
8
meant to form spacers
9
of the different transistors, which etching is performed after the LDD
N
and LDD
P
implantations. Indeed, this etching also etches the surface of substrate
1
, which deteriorates lightly-doped shallow underlying regions
5
and
7
. This is particularly disturbing on either side of the gates of the high voltage transistors where lightly-doped shallow region
5
/
7
has to remain in place. It should be noted that this disadvantage is even more serious in the case of submicronic technologies in which the lightly-doped regions are particularly shallow.
Another disadvantage of this method is that the mask of definition of the silicided areas is not, at the level of the high voltage transistors, self-aligned with source/drain contact regions
11
/
13
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing high and low voltage MOS transistors on a same semiconductor substrate which overcomes these disadvantages.
Another object of the present invention is to provide a method of manufacturing high and low voltage MOS transistors on the same semiconductor substrate which is of more easy implementation, lower cost, and which reduces the number of manufacturing steps.
To achieve these and other objects, the present invention provides a method of manufacturing integrated circuits including high and low voltage MOS transistors of same type, this method including the steps of forming insulated gate structures, forming lightly-doped drain/source regions, depositing an insulating layer, and further including the steps of:
1) forming a mask above the gates of the high voltage transistors which extends laterally beyond said gates;
2) etching the insulating layer to leave spacers on the edges of the low voltage transistor gates;
3) implanting a dopant adapted to forming heavily-doped drain/source contact regions of the high and low voltage transistors; and
4) forming in a self-aligned way a metal silicide layer on the drain/source contact regions of all transistors, as well as on the gate contacts of the low voltage transistors.
According to an embodiment of the present invention, the sequence of steps 1) to 3) is implemented twice, once for each series of MOS transistors of a given conductivity type.
According to an embodiment of the present invention, at steps 2) and 3), oxide areas are left in place in selected regions.
According to an embodiment of the present invention, the method applies to technological lines in which the minimum dimension of a pattern is under 1 &mgr;m.
The foregoing objects, features and advantages of the pr
Everhart Caridad
Lee Calvin
Morris James H.
Steinberg Mark
STMicroelectronics S.A.
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