Hierarchical scan selection

Details Hierarchical scan selection Hierarchical scan selection

1988-12-08

1989-10-03

Atkinson, Charles E.

Excavating

G01R 3128

Patent

active

048721697

ABSTRACT:
A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the design via serial scan operations. The present invention allows a continuous scan path to be compressed or expanded so that the scan path only passes through the desired logic element(s) to be tested. Devices connected on the serial scan path (or ring) can be selected or deselected thus allowing the serial path to either flow through or bypass a given logic circuit's internal scan path. The invention can be used to create a hierarchical scan network consisting of a primary scan ring from which a multiplicity of scan sub-rings may be accessed.

REFERENCES:
patent: 4597042 (1986-06-01), d'Angeac
patent: 4621363 (1986-11-01), Blum
patent: 4680733 (1987-07-01), Duforestel
patent: 4698588 (1987-10-01), Hwang
patent: 4701921 (1987-10-01), Powell
patent: 4710931 (1987-12-01), Bellay
patent: 4710933 (1987-12-01), Powell

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