Hierarchical memory correction system and method

Details Hierarchical memory correction system and method Hierarchical memory correction system and method

2007-06-05

2007-06-05

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000

Reexamination Certificate

active

11215107

ABSTRACT:
A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a plurality of memory devices. A first error correction engine is provided for correcting device-level errors associated with a specific memory device and a second error correction engine for correcting errors at a memory module level, wherein the first and second error correction engines are operable in association with a memory controller operably coupled to the plurality of memory modules.

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