Hierarchical analog IC placement subject to symmetry,...

Details Hierarchical analog IC placement subject to symmetry,... Hierarchical analog IC placement subject to symmetry,...

2011-01-18

2011-01-18

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07873928

ABSTRACT:
A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement.

REFERENCES:
patent: 6550046 (2003-04-01), Balasa et al.
patent: 7093220 (2006-08-01), Fallon et al.
patent: 7739646 (2010-06-01), Lin et al.
patent: 2008/0092099 (2008-04-01), Lin et al.
Lin et al., “Analog Placement Based on Symmetry-Island Formulation,” IEEE Trans. on CAD of ICs and Systems, vol. 28, No. 6, Jun. 2009, pp. 791-804.
Lin et al., “Analog Placement Based on Novel Symmetry-Island Formulation,” DAC '07, Jun. 4-7, 2007, pp. 465-470.
Balasa, “Modeling Non-Slicing Floorplans with Binary Trees,” 2000 IEEE, pp. 13-16.
Balasa et al., “Efficient Solution Space Exploration Based on Segment Trees in Analog Placement with Symmetry Constraints,” 2002 IEEE, pp. 497-502.
Balasa et al., “Symmetry Within the Sequence-Pair Representation in the Context of Placement for Analog Design,” IEEE Trans. on CAD of ICs and Systems, vol. 19, No. 7, Jul. 2000, pp. 721-731.
Balasa et al., “On the Exploration of the Solution Space in Analog Placement With Symmetry Constraints,” IEEE Trans. on CAD of ICs and Systems, vol. 23, No. 2, Feb. 2004, pp. 177-191.
Balasa et al., “Using Red-Black Interval Trees in Device-Level Analog Placement with Symmetry Constraints,” 2003 IEEE, pp. 777-782.
Balasa, “Device-Level Placement for Analog Layout: An Opportunity for Non-Slicing Topological Representations,” 2001 IEEE, pp. 281-286.
Chang et al., “B*-Trees: A New Representation for Non-Slicing Floorplans,” DAC 2000, pp. 458-463.
Lin et al., A Matching-based Placement and Routing System for Analog Design, 2007 IEEE, 4 pages.
Ma et al., “Analog Placement with Common Centroid Constraints,” 2007 IEEE, pp. 579-585.
Kouda et al., “Improved Method of Cell Placement with Symmetry Constraints for Analog IC Layout Design,” ISPD '06, Apr. 9-12, 2006, pp. 192-199.
Chen et al., “Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing,” IEEE Trans. on CAD of ICs and Systems, No. 25, vol. 4, Apr. 2006, pp. 637-650.
Cohn et al “KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing,” IEEE Journal of Solid-State Circuits, vol. 26, No. 3, Mar. 1991, pp. 330-342.
He et al., “Analog Placement Design with Constraints of Multiple Symmetry Groups,” Canadian Conference on Electrical and Computer Engineering, May 3-6, 2009, pp. 1204-1207.
Koda et al., “Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout,” IEEE Trans. on CAD of ICs and Systems, vol. 26, No. 4, Apr. 2007, pp. 659-668.
Krishnamoorthy et al., “Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design,” 2007 IEEE, pp. 2032-2035.
Lin et al., “LAKE: A Performance-Driven Analog CMOS Cell Layout Generator,” 1994 IEEE, pp. 564-569.
Lampaert et al., “A Performance-Driven Placement Tool for Analog Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. 30, No. 7, Jul. 1995, pp. 773-780.
Lin et al., Placement with Symmetry Constraints for Analog Layout Design Using TCG-S, ASP-DAC 2005EE, pp. 1135-1138.
Lin et al., ′Module placement with boundary constraints using B*-trees, IEE Proc.-Circuits, Devices, Syst., vol. 149, No. 4, Aug. 2002, pp. 251-256.
Lin et al., “Analog Placement Based on Hierarchical Module Clustering,” DAC 2008, Jun. 8-13, pp. 50-55.
Malavasi et al., “Automation of IC Layout with Analog Constraints,” IEEE Trans. on CAD of ICs and Systems, vol. 15, No. 8, Aug. 1996, pp. 923-942.
Prieto et al., “A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog ICs,” 1997 IEEE, pp. 389-394.
Tam et al., “Analog Placement with Symmetry and Other Placement Constraints,” ICCAD '06, pp. 349-354.
Wu et al., “Rectilinear Block Placement Using B*-Trees,” ACM Trans. on Design Automation of Electronic Systems, vol. 8, No. 2, Apr. 2003, pp. 188-202.
Wu et al., “Placement with Alignment and Performance Constraints Using the B*-tree Representation,”2004 Proc. IEEE Int'l Conference on Cumputer Design (ICCD'04), 4 pages.

Affiliated with

Also associated with

Rating

Hierarchical analog IC placement subject to symmetry,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical analog IC placement subject to symmetry,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical analog IC placement subject to symmetry,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2645404