Hiding error detecting/correcting latency in dynamic random...

Details Hiding error detecting/correcting latency in dynamic random... Hiding error detecting/correcting latency in dynamic random...

2005-02-08

2005-02-08

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189040

Reexamination Certificate

active

06853602

ABSTRACT:
System and method for hiding error detecting and correcting latency in a dynamic random access memory refresh cycle. A preferred embodiment comprises in a first memory refresh cycle, detecting the presence of an error in information retrieved from a memory element and in a second memory refresh cycle, writing corrected information back to the memory element containing the erroneous information, wherein the second memory refresh cycle is a memory refresh cycle immediately following the first memory refresh cycle.

REFERENCES:
patent: 6560725 (2003-05-01), Longwell et al.

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