Cleaning and liquid contact with solids – Processes – Including application of electrical radiant or wave energy...
Reexamination Certificate
1998-06-16
2001-04-24
Gulakowski, Randy (Department: 1746)
Cleaning and liquid contact with solids
Processes
Including application of electrical radiant or wave energy...
C134S001300, C216S058000, C216S079000
Reexamination Certificate
active
06221168
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to treating microelectronics substrates. In particular, the invention provides a method for treating substrates whereby the surface generated has improved characteristics. The resulting surfaces are particularly useful for subsequent processing steps including deposition of thin films.
BACKGROUND OF THE INVENTION
Deposition of epitaxial silicon is one of many thin film deposition processes used in the manufacture of microelectronic devices. While this process is currently important, we anticipate that it will grow in importance as future generations of devices require selective deposition of epitaxial silicon layers. The ideal starting surface for deposition of epitaxial silicon is a completely oxygen- and carbon-free silicon surface. Any oxygen content in the starting surface will result in defects in the deposited silicon. This type of surface is often equated with a hydrogen-terminated surface, although the presence of fluorine and chlorine atoms at the surface may be acceptable as long as the oxygen concentration is suitably low.
Current processes for epitaxial silicon deposition require a pre-clean to remove any oxide on the areas targeted for deposition. The pre-clean can use either an aqueous solution of hydrogen fluoride (HF), or a gas phase HF oxide removal process such as those disclosed in U.S. Pat. No. 4,749,440 (Blackwood et al.), U.S. Pat. No. 5,022,961 (Izumi et al.), or U.S. Pat. No. 5,234,540 (Grant et al.). This is followed by a hydrogen bake at temperatures over 800° C. for several minutes to provide the best possible surface for the subsequent deposition.
The above process sequence is effective for producing an epitaxial silicon layer, but the high temperature hydrogen bake poses potential problems due to diffusion of dopant atoms. In many selective epitaxy applications, at least a portion of the eventual source and drain dopant profiles will be in place prior to the selective epitaxy. Once the dopant profiles are in place, any steps which heat the wafer to high temperatures will allow diffusion of dopant atoms which will reduce the sharpness of the dopant profiles. This can lead to degradation of device performance and limit the ability to reduce the size of a device. Thus, it is desirable to minimize the number and length of high temperature steps once dopant profiles are in place.
A cleaning step which removes all of the oxide from the silicon substrate without roughening the surface may provide a suitable surface for deposition without performing a hydrogen bake. One potential method for eliminating the hydrogen bake is to perform a gas phase HF oxide removal step immediately prior to starting epitaxial deposition. A completely gas phase HF removal step has no rinse, which prevents any regrowth of native oxide on the surface. A completely gas phase HF removal step may also be performed at reduced pressures, making the process compatible with other vacuum equipment. This would allow the HF process to either be carried out in the deposition chamber itself or in a separate chamber directly connected to the deposition chamber. This eliminates the need for exposure to atmosphere during transfer of the wafer to the deposition chamber which also reduces the likelihood for native oxide regrowth.
Previous attempts to use a completely gas phase HF oxide removal step to eliminate the need for a hydrogen pre-bake have shown only limited success.
Iyer et al.,
Appl. Phys. Lett
., Vol. 57, p. 893 (1990), studied gas phase HF oxide removal without a hydrogen pre-bake as a clean prior to both molecular beam epitaxy (MBE) and ultra high vacuum chemical vapor deposition (UHV/CVD) of silicon. The MBE depositions were carried out at 550° C., while the UHV/CVD experiments were performed between 700 and 850° C. However, the maximum silicon deposition rate in these experiments was on the order of 50 angstroms/minute, which is an order of magnitude slower than the rate needed in practical single wafer deposition tools.
Kuiper et al.,
Mat. Res. Soc. Symp. Proc
., Vol. 259, p. 473 (1992), also reported deposition of epitaxial silicon after gas phase HF treatment. They achieved reasonable growth rates at deposition temperatures between 700 and 750° C., but they reported a defect density of 1,500 defects/cm
2
in the resulting epitaxial layer.
Aoyama et al.,
J. Electrochem. Soc
., Vol. 140, p. 366 (1993), employed F
2
/Ar in the presence of ultraviolet (UV) light to prepare silicon substrates for epitaxial silicon deposition. Without using an H
2
pre-bake, they deposited silicon at 650° C. but only achieved a silicon deposition rate of 75 angstroms/minute.
Therefore a need remains for a process for surface preparation which can be run at commercially practical rates and effectively reduce the thermal load needed to put the surface in condition for an epitaxial silicon deposition.
SUMMARY OF INVENTION
It has now been unexpectedly discovered that a known gas phase etch process using HF and isopropyl alcohol (IPA), when employed over a very narrow range of process condition parameters, can produce the desired improved surface condition under conditions and rates found in current industrial tools. The resulting surface is useful whenever it is desirable to produce a silicon surface with a minimum amount of residual oxygen, especially for preparing a silicon surface for a subsequent deposition of epitaxial silicon.
The etch reaction process of the invention is run at a pressure of from 125 to 175 torr pressure using a gas mixture of HF, isopropyl alcohol and nitrogen in a volume ratio of about 20-30:1:20-30, respectively.
The invention provides a silicon surface which gives remarkably lower incidence of light point defects after epitaxial silicon deposition. Thus, the present invention allows for reduction of the number of high temperature steps and/or the length of these steps in a subsequent deposition process. In particular, this improved process allows for a lower temperature and/or shorter hydrogen bake prior to deposition, and in some cases may allow for elimination of the hydrogen bake step entirely. A further aspect of the present invention, therefore is a process for depositing a film, especially an epitaxial silicon film, in which prior to the deposition step, the substrate surface is subjected to an HF/IPA etch process run at a pressure of from 125 to 175 torr pressure using a gas mixture of HF, isopropyl alcohol and nitrogen in a volume ratio of about 20-30:1:20-30, respectively.
REFERENCES:
patent: 4746397 (1988-05-01), Maeda et al.
patent: 5022961 (1991-06-01), Izumi et al.
patent: 5294568 (1994-03-01), McNeilly et al.
patent: 5439553 (1995-08-01), Grant et al.
patent: 5470799 (1995-11-01), Itoh et al.
patent: 5580421 (1996-12-01), Hiatt et al.
patent: 5814156 (1998-09-01), Elliott et al.
patent: 5922219 (1999-07-01), Fayfield et al.
patent: 6015759 (2000-01-01), Khan et al.
patent: 98/19336 (1998-05-01), None
“Vapor HF Etching For Low Temperature Silicon Epitaxy” by Christopher P. D'Emic, et al,Mat. Res. Soc. Symp. Proc.vol. 259, 1992 Materials Research Society., pp. 479-485.
“A Complementary Wafer Cleaning and Growth Process for Low Temperature, Defect Free, Selective Silicon Epitaxy” by Jon T. Fitch et al,Mat. Res. Soc. Symp. Proc.vol. 259, 1992 Materials Research Society, pp 487-492.
“Optimization of Si-Wafer Cleaning and the Use of Buffer-Layers For Epitaxial Growth of Sige-Layers by VLPCVD ATT=650 C.”, by Matty R. Caymax et al,Mat. Res. Soc. Symp. Proc.vol. 259, 1992 Materials Research Society, pp. 461-466.
“Room-Temperature HF Vapour-Phase Cleaning For LPCVD EPI of Si and SIGe”, by A.E.T. Kuiper et al,Mat. Res. Soc. Symp. Proc.vol. 259, 1992 Materials Research Society., pp. 473-478.
“Low-temperature silicon cleaning via hydrogen passivation and conditions for epitaxy” by S.S. Lyer et al in Appl. Phys. Lett. 57(9), Aug. 27, 1990, pp.893-895.
“Low-temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition” by B. S. Meyerson, inAppl. Phys. Lett.48(12), Mar. 24, 1986, pp.797-799.
“Low-Temper
Carter Lawrence E.
Fayfield Robert T.
Schwab Brent
Chaudhry Saeed T.
FSI International Inc.
Gulakowski Randy
Vidas Arrett & Steinkraus
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