Hexagonally symmetric integrated circuit cell

Details Hexagonally symmetric integrated circuit cell Hexagonally symmetric integrated circuit cell

2000-04-03

2002-01-29

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S240000, C438S241000, C438S242000, C438S253000, C438S254000, C438S255000, C438S256000, C438S397000, C438S398000, C438S399000, C257S905000

Reexamination Certificate

active

06342420

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of integrated circuits, and more particularly, to circuits such as a dynamic random access memory cell and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with dynamic access random memory (DRAM) cells, as an example.
As is well known in the art of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area is defined by the geometries and sizes of the active components disposed in the wafer substrate. Active components include gate electrodes in metal-oxide semiconductors (MOS) and diffused regions such as MOS source and drain regions and bipolar emitters, collectors and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular equipment used for processing the integrated circuit.
A significant problem of current photolithographic techniques as applied to very-large-scale integration (VLSI) as more and more layers are added, is that additional steps add additional complexity to the creation of circuits on the wafer surface. The resolution of small image sizes in photolithography becomes more difficult due to light reflection and the thinning of the photoresist during processing.
As a two dimensional process used to achieve a three dimensional structure, the goal of photolithographic patterning is to establish the horizontal and vertical dimensions of the various devices and circuits used to create a pattern that meets design requirements, such as, the correct alignment of circuit patterns on the wafer surface. As line widths shrink, photolithography of patterns down to the nanometer level and smaller approach the limits of resolution of present equipment. These nanometer width lines become increasingly more difficult to pattern because of the need to isolate the integrated circuit components.
A DRAM cell consists of a transistor and a capacitor. A bitline and a wordline are connected to one of the transistor source/drain and its gate, with the other source/drain being connected to the capacitor. As the density of DRAM cells on a silicon chip increases, DRAM cells having three dimensional structures, such as stacked capacitors, have been developed to meet the increased need for miniaturization. The use of stacked three dimensional structures, for example, allows the DRAM designer to maximize the capacitance of storage nodes within the limited area of the DRAM cell.
SUMMARY OF THE INVENTION
What is needed is a structure and method for using current integrated circuit processing techniques and manufacturing equipment that meet the demands of VLSI integrated circuits. Also needed, is an improvement in the design of masking patterns that can be used with laser-based step lithography that provides the isolation required for DRAM cell production. These masking and DRAM cell designs must conform to current equipment and manufacturing techniques, and at the same time, provide the required increase in DRAM chip capacity.
Large distances between bitline contacts and storage node contacts cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.
The present invention is directed to a DRAM circuit comprising, a first source/drain and a bitline electrically connected to the first source/drain by a bitline contact. At least six storage node contacts are hexagonally disposed surrounding the bitline contact. The at least six storage nodes electrically connected to a second source/drain by at least six storage node contacts. In one embodiment the DRAM circuit further comprises a wordline electrically connected to a field effect transistor, the wordline being disposed at an angle to the bitline.
In one embodiment the area covered by an individual DRAM cell is calculated by the formula:
3/4{square root over (3)}×
h×h=
8
f
2
where f is a design rule value and h is the closest distance between a storage node contact and a bitline contact. The diameter of said bitline can be h/2, as can be the diameter of said storage node contact is h/2. The wordline for use with the invention can comprise a centerline extending through the wordline and protrusions that extend from the centerline to form the transistor gate. The protrusions of the wordline can have an area calculated by the formula:
{square root over (3)}/2*
h
−3/10
*h=area
wherein h is the closest distance between, e.g., a storage node contacts and a bitline contact.
The storage node can have an area defined by the following formula:
(6−3{square root over (3)}/2)
ht+
{square root over (3)}/4(1−{square root over (3)}/4)
2
h
2
wherein h is the closest distance between, e.g., a storage node contacts and a bitline contact, and t is the dielectric constant for a capacitor.
The present invention is also directed to a method for fabricating DRAM cells on a silicon wafer comprising the steps of simultaneously forming six storage node contacts disposed surrounding a bitline contact, disposing a wordline to form at least one field effect transistor gate, forming six storage nodes surrounding a bitline in a hexagonal manner, contacting each of the storage nodes with a storage node contact and forming a capacitor with the storage node contacts.
In yet another embodiment, a method of fabricating an integrated circuit comprising simultaneously forming at least seven hexagonally arranged via contacts, the lower end of two of the via contacts electrically connect to first and second circuit elements. In one embodiment, the first type of circuit element is a first source/drain of a transistor. In another embodiment, the second type of circuit element is a second source/drain of the transistor. Alternatively, the second type of circuit element is the gate of a transistor.


REFERENCES:
patent: 5442212 (1995-08-01), Eimori
patent: 5998256 (1999-12-01), Juengling

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