Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-10-11
2005-10-11
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S022000, C438S046000, C438S047000, C438S590000, C257S094000, C257S102000, C257S103000, C257S183000, C257S192000
Reexamination Certificate
active
06953729
ABSTRACT:
In a heterojunction FET in which source and drain areas are formed by carrying out high temperature annealing process after carrying out ion implantation in areas to be formed into source and drain areas, conventionally, the N-type carrier supply layer and the N-type active layer are doped with Si. In place of doping with Si, doping with Se or Te is adopted. Thereby, in high temperature annealing process for activating the ion implanted areas, which serves as source and drain areas, unlike the Si donor, inactivation of donor due to reaction with F-atoms occurs scarcely with respect to the diffusion of F-atoms on the surface of the epitaxial substrate, which adhered during the process. Further, since the Se and Te are impurities from VI-family, when the Se or Te occupies any grid position of atoms from III-family or V-family, the Se or Te serves as the donor. Accordingly, a high performance heterojunction FET of little deterioration of the FET characteristics can be obtained.
REFERENCES:
patent: 3914785 (1975-10-01), Ketchow
patent: 3923875 (1975-12-01), Rose et al.
patent: 4188710 (1980-02-01), Davey et al.
patent: 4471366 (1984-09-01), Delagebeaudeuf et al.
patent: 4593301 (1986-06-01), Inata et al.
patent: 4673959 (1987-06-01), Shiraki et al.
patent: 5060031 (1991-10-01), Abrokwah et al.
patent: 5144410 (1992-09-01), Johnson
patent: 5381027 (1995-01-01), Usagawa et al.
patent: 5480829 (1996-01-01), Abrokwah et al.
patent: 5825052 (1998-10-01), Shakuda
patent: 5907164 (1999-05-01), Nakayama
patent: 6194747 (2001-02-01), Onda
patent: 03250742 (1991-11-01), None
J. Abrokwah, et al., “A Manufactuable Complementary GaAs Process”, IEEE, 1993, pp. 127-130.
N. Hayafuji, et al., “Thermal Stability of AllnAs/GainAs/InP Heterostructures”, American Institute of Physics, Feb. 1995, pp. 863-865.
Kato Yoshiaki
Kojima Keisuke
Tamura Akiyoshi
Huynh Andy
Matsushita Electric - Industrial Co., Ltd.
Stevens Davis Miller & Mosher LLP
LandOfFree
Heterojunction field effect transistor and manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Heterojunction field effect transistor and manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Heterojunction field effect transistor and manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3483711