Hetero-integrated strained silicon n- and p-MOSFETs

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S520000, C438S149000, C438S938000

Reexamination Certificate

active

10978715

ABSTRACT:
The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

REFERENCES:
patent: 6562703 (2003-05-01), Maa et al.
patent: 6593625 (2003-07-01), Christiansen et al.
patent: 6709903 (2004-03-01), Christiansen et al.
patent: 2003/0127696 (2003-07-01), Lee
patent: 2004/0087119 (2004-05-01), Maa et al.
patent: 2004/0214407 (2004-10-01), Westhoff et al.

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