Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-18
2004-12-21
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S057000, C257S066000
Reexamination Certificate
active
06833587
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to improved Silicon-on-Insulator (SOI) devices. More particularly, the present invention relates to methods for removing heat from Silicon-on-Insulator devices and devices having such characteristics.
BACKGROUND OF THE INVENTION
Silicon-on-Insulator (SOI) technology is of growing importance in the field of integrated circuits. SOI technology involves forming transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. More particularly, SOI technology is characterized by the formation of a thin silicon layer (device region) for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources and drains are formed, for example, by implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor layer structure.
Such structures provide a significant gain in performance compared to bulk silicon structures by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects. This is because no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current. Devices, such as metal oxide silicon field effect transistors (MOSFET), have a number of advantages when formed on SOI wafers versus bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N
+
to P
+
spacing and hence higher packing density due to ease of isolation; absence of latch-up; lower voltage applications; and higher “soft error” upset immunity (i.e.; the immunity to the effects of alpha particle strikes).
Although there are significant advantages associated with SOI technology, there are significant disadvantages as well. For example, poor heat removal from devices on an SOI substrate is a significant disadvantage. Electrical devices generate heat, and the inability to remove or dissipate the heat results in poor and/or inconsistent performance of the electrical devices, or even in some instances device and/or substrate degradation.
There is poor heat removal for devices on SOI substrates primarily because of the oxide insulation layer. More specifically, the oxide insulation layer has a markedly lower thermal conductivity than the thermal conductivity of conventional bulk silicon (typically used as semiconductor substrates), which typically surrounds semiconductor devices. For example, the thermal a conductivity of silicon dioxide is about 1.4 W/m° C., while the thermal conductivity of conventional bulk silicon is about 150 W/m° C. As a result, the buried oxide layer can undesirably thermally insulate the device region in SOI substrates.
In view of the aforementioned disadvantages, there is a need for SOI devices of improved quality, particularly SOI devices having improved heat removal characteristics, and more efficient methods of making such SOI devices.
SUMMARY OF THE INVENTION
As a result of the present invention, an SOI substrate having improved heat removal characteristics (from the device layer) is provided. By forming an SOI substrate according to the present invention, improved performance of devices subsequently formed on the SOI substrate is facilitated. Moreover, forming an SOI substrate in accordance with the present invention does not degrade or deleteriously effect the advantageous properties and characteristics commonly associated with SOI technology (improved speed performance at higher-operating frequencies, higher packing density, absence of latch-up, lower voltage applications, and higher “soft error” upset immunity).
According to an aspect of the invention, a silicon-on-insulator substrate is disclosed which comprises: a silicon substrate layer, a first insulation layer over the silicon substrate layer; a conductive layer over the first insulation layer comprising at least one metal or metal silicide over the first insulation layer; a second insulation layer over the conductive layer; a silicon device layer comprising silicon over the second insulation layer; and at least one conductive plug through the silicon substrate layer and the first insulation layer contacting the conductive layer, or at least one conductive plug through the silicon device layer and the second insulation layer contacting the conductive layer.
According to another aspect of the invention, a method of forming a silicon-on-insulator substrate is disclosed which comprises the steps of: providing a silicon substrate; depositing a first insulation layer over the silicon substrate; forming a conductive layer over the first insulation layer to a first structure; providing a second structure comprising a silicon device layer and a second insulation layer; bonding the first structure and the second structure together so that the conductive layer is located between the first and second insulation layers; and removing a portion of the silicon device layer thereby providing the silicon-on-insulator substrate having two discrete insulation layers.
According to another aspect of the invention, a method of facilitating heat removal from a device layer of a silicon-on-insulator substrate comprising bulk silicon, a first insulation layer over the bulk silicon, a second insulation layer over the conductive layer, and a silicon device layer over the second insulation layer, is disclosed which comprises: forming a conductive layer between the first and second insulation layers; and forming at least one conductive plug through the bulk silicon and the first insulation layer so as to contact the conductive layer.
According to yet another aspect of the invention, a method of facilitating heat removal from a device layer of a silicon-on-insulator substrate comprising bulk silicon, a first insulation layer over the bulk silicon, a second insulation layer over the conductive layer, and a silicon device layer over the second insulation layer, is disclosed which comprises: forming a conductive layer between the first and second insulation layers; and forming at least one conductive plug through the silicon device layer and the second insulation layer so as to contact the conductive layer.
Due in part to the above methods, silicon-on-insulator substrates can be formed which have improved heat transfer capabilities. Additionally, devices formed from such silicon-on-insulator substrates yield SOI devices of improved quality and reliability.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 6586284 (2003-07-01), Kim
patent: 6627953 (2003-09-01), Vu et al.
patent: 2001/0033001 (2001-10-01), Kato
patent: 2002/0020874 (2002-02-01), Gimonet
Advanced Micro Devices , Inc.
Ngo Ngan V.
Renner , Otto, Boisselle & Sklar, LLP
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