Hardware efficient CRC generator for high speed...

Details Hardware efficient CRC generator for high speed... Hardware efficient CRC generator for high speed...

2008-05-06

2008-05-06

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000, C714S781000

Reexamination Certificate

active

11285761

ABSTRACT:
A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123nddegree generator polynomial and subsequently dividing the remainder of the first division by a 32nddegree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123nddegree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)thbyte being used in the division of the ithbyte.

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