Hardware design for majority voting, and testing and...

Details Hardware design for majority voting, and testing and... Hardware design for majority voting, and testing and...

2000-04-07

2001-06-26

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C326S035000

Reexamination Certificate

active

06253348

ABSTRACT:

BACKGROUND
The present invention generally relates to majority voting of signals, and in particular to a majority voting circuit, and also to testing and maintenance of majority voting.
Majority voting is frequently utilized in a wide variety of technical applications in many technical fields. In particular, majority voting is of great importance in fault tolerant or redundant systems. Examples of such systems are clock generating systems and data processing systems.
In general, a majority voting circuit accepts a plurality of logical input signals to generate a logical output signal that is representative of the majority vote of the input signals. In the case of three input signals, the majority vote is generally performed according to the following simple Boolean expression: (A AND B) OR (A AND C) OR (B AND C), where A, B and C represent the logical levels of the signals that are input to the majority voting circuit. If all three input signals are present, the majority voting circuit sets the majority voted output signal to a high level if a majority of the three incoming signals are at high level, otherwise the output signal will be set to a low level. In the case of a single faulty input signal, the majority voting circuit will still be able to generate a correct output signal.
However, conventional majority voting circuits have problems in effectively handling more than one faulty input signal; especially when the input signals are periodic.
U.S. Pat. No. 4,583,224 issued to Ishii et al. on Apr. 15, 1986 relates to redundancy control, and in particular to fault tolerable redundancy control using majority vote logic. There is disclosed a redundant control system in which three control signals from three equivalent signal processors are subjected to a majority vote operation in order to generate a single majority voted control signal. The majority voted control signal is used for controlling an apparatus or system such as an atomic power plant. The control signals are compared to each other, and if one of the control signals differs from the other control signals, then the different control signal is considered as abnormal and an error detection signal, corresponding to the abnormal signal, is generated. There is also provided means for generating a set signal of a predetermined level, “0” or “1”. A switching device receives the control signals, the error detection signal and the set signal for forwarding the control signals that are not associated with the error detection signal to a majority logic circuit, and for forwarding the set signal to the majority logic circuit instead of the abnormal control signal. When one of the three inputs to the majority logic is fixed to have the set level of “1”, the logic circuit is equivalent to an OR gate applied with the remaining inputs. On the other hand, when one of the three inputs is fixed to have the set level of “0”, the logic circuit is equivalent to an AND gate applied with the remaining inputs.
Apparently, the control system in U.S. Pat. No. 4,583,224 is customized for static signals, and fail-safe control operation can be continued after the occurrence of faults in two of the three control channels only by previously determining which logical level “0” or “1” that is to be substituted for the abnormal control signal.
SUMMARY
It is a general object of the invention to provide an improved and robust hardware design for majority voting of signals.
In particular, it is an object to provide circuitry which controls the majority voting and which corrects for faulty input signals. The majority voting must work such that a well defined and correct output signal is generated no matter if one or more input signals are faulty. If, as an example, majority voting is performed on dynamic or periodic signals such as clock signals, and one or more of the clock signals have stopped, then a correct output clock should be generated no matter if the input clock signals have stopped at a high or low logical level.
A further object is to provide a clock generating system and a corresponding method based on the improved majority vote hardware design.
Still another object of the invention is to enable testing and maintenance of majority voting. To this end, majority vote test and maintenance methods as well as corresponding devices are provided. For maintenance reasons, it is desirable to be able to check that the majority voting functionality is actually working, without causing disturbances in the system.
These and other objects are solved by the invention as defined below.
The invention offers the following advantages:
A robust majority vote functionality;
The system, such as a clock system in a telecommunication switch, in which the majority vote logic is used becomes less sensitive to disturbances or malfunctions;
Maintenance tests can be performed without causing disturbances, which in turn means that this kind of testing can be made much more often, even on a routine basis; and
Improved reliability and service availability.
Other advantages offered by the present invention will be appreciated upon reading of the below description of the embodiments of the invention.


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