Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2008-01-18
2009-02-03
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S673000, C438S736000, C438S508000, C257SE21246
Reexamination Certificate
active
07485582
ABSTRACT:
The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.
REFERENCES:
patent: 5481135 (1996-01-01), Chandra et al.
patent: 6737727 (2004-05-01), Gates et al.
patent: 6740539 (2004-05-01), Conti et al.
patent: 2004/0203223 (2004-10-01), Guo et al.
Gates Stephen M.
Lane Michael
Liu Xiao H.
McGahay Vincent J.
Mehta Sanjay C.
International Business Machines - Corporation
Pham Thanh V
Scully , Scott, Murphy & Presser, P.C.
Trepp, Esq. Robert M.
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