Hardened current mode logic (CML) voter circuit, system and...

Electronic digital logic circuitry – Reliability – Redundant

Reexamination Certificate

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C326S095000, C327S144000

Reexamination Certificate

active

07965098

ABSTRACT:
A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

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patent: 2007/0236246 (2007-10-01), Roper
ISA/US, International Search Report, International Application No. PCT/US2008/086291 Filed Dec. 10, 2008, Dated Feb. 12, 2009, 1 page.
ISA/US, Written Opinion, International Application No. PCT/US2008/086291 Filed Dec. 10, 2008, Dated Feb. 12, 2009, 7 page.

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