Baths – closets – sinks – and spittoons – Tubs – Particular construction or configuration details
Reexamination Certificate
2000-09-27
2002-02-12
Elms, Richard (Department: 2824)
Baths, closets, sinks, and spittoons
Tubs
Particular construction or configuration details
C438S545000, C438S700000, C438S763000, C204S192350, C156S074000
Reexamination Certificate
active
06345399
ABSTRACT:
DESCRIPTION
1. Field of the Invention
The present invention relates to semiconductor device processing in which both lithography and etching are employed in forming a pattern in at least one material layer of a semiconductor structure. More particularly, the present invention is directed to a process whereby a thin, compressive hard mask is placed between a resist film and a non-compressive material layer being patterned which hard mask prevents the propagation of microfissures from the resist film into the underlying material layer. By employing a selective etch chemistry in conjunction with the inventive hard mask, the damage of the resist, i.e., microfissures, is not transferred through the hard mask, and surface roughness of the underlying non-compressive material layer is reduced.
2. Background of the Invention
The extension of 248 nm lithography in the semiconductor industry has in many cases led to the introduction of more sensitive photoresists. These photoresists have demonstrated poor performance with traditional etch processes with regard to image integrity via resist damage. The level of the photoresist damage has been found to vary inversely with the selectivity of the etch process to the photoresist. Processes with highly polymerizing chemistries, which are highly selective to photoresist, tend to result in increased levels of photoresist damage. For example,
FIGS. 1 and 2
show results from a highly selective oxide etch process on a typical oxide stack (7000 Å boron silicate glass (BSG))
10
containing photoresist
12
. Specifically,
FIG. 1
is a cross-section of a structure through a prior art patterning process before resist strip showing a substantial amount of photoresist
12
remaining after etching. In
FIG. 2
, the top of the oxide is shown following resist stripping. The roughness
16
around the edges of the opened pattern
14
will be transferred into subsequent levels, resulting in degraded device performance due to leakage and other concerns.
The inverse relationship between the level of damage to the top of the image and the photoresist selectivity has considerably narrowed (or in some cases removed entirely) the available process window for deep oxide etch. As the pitch for critical levels decreases, the amount of available photoresist is also reduced due to the constraints of optical lithography. This reduction in photoresist thickness requires the application of a more selective etch process. However, as the selectivity of the etch process is increased, the quality of the patterned image is substantially degraded, leading to unacceptable microcrevices (herein referred to as microfissures) in the etched material.
For example, the current deep trench mask open etches cannot meet the simultaneous requirements of resist selectivity and image integrity for very small ground rules, e.g., 150 nm or less. Another example is the current local interconnect level shorts yield degradation that results from very poor image integrity. The inverse relationship between the generation of microfissures and photoresist selectivity can be understood by a thermal stress model of the photoresist during a selective wet etch process, See FIG.
3
. The photoresist
12
which includes polymer capping layer
13
is heated during the oxide etch process by ion and radical bombardment. The primary cooling mechanism for the photoresist is through evaporation of the photoresist etched products. When a highly polymerizing chemistry is used, the evaporative cooling of the photoresist is hampered. The resulting temperature increase in the resist film may lead to increased breakdown in the resist polymer chains, and subsequent cracking
18
of the resist surface, See FIG.
4
. These cracks in the resist surface lead to fissures near the edges of open features, which expose the underlying surface to the etch chemistry.
In the traditional scheme described above, the oxide surface is exposed to the plasma wherever microfissures form in the photoresist. Because the prior art etch is designed to etch oxide, i.e., have a high oxide etch rate, the crevices in the resist are transferred into the underlying film.
In view of the above drawbacks with prior art patterning processes which include at least lithography and etching, there is a continued need to develop a new and improved method which substantially prevents the transfer of microfissures from the photoresist to the underlying material being patterned.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of forming a pattern, such as a deep trench or local interconnect, in a non-compressive material layer requiring patterning whereby the method prevents the formation of microfissures, e.g., striations, in the final patterned material layer.
Another object of the present invention is to provide a method wherein the roughness about the patterned opening has been substantially reduced.
A further object of the present invention is to provide a method wherein the microfissures are prevented from propagating from the photoresist into the underlying material layer being patterned using a highly selective etch process.
A still further object of the present invention is to provide a method wherein the thickness of the photoresist may, in some instances, be substantially reduced from thicknesses that are typically employed in prior art patterning processes.
These and other objects and advantages are achieved in the present invention by forming a compressive hard mask between a photoresist layer and a non-compressive material layer to be patterned by etching, wherein the hard mask comprises a material that substantially prevents the transfer of microfissures that develop in the photoresist to the underlying material layer during etching.
Specifically, the present invention is directed to a method of substantially preventing the transfer of photoresist microfissures, e.g., striations, to a material layer to be patterned by lithography and etching, said method comprising:
(a) forming a compressive hard mask on a surface of a non-compressive material layer that is to be patterned by lithography and etching;
(b) forming a patterned photoresist on said hard mask, wherein a portion of said hard mask is exposed;
(c) removing said exposed portion of said hard mask so as to expose a portion of said non-compressive material layer; and
(d) transferring said pattern from said patterned photoresist to said exposed portion of said material layer by etching, wherein said hard mask is selective to said etching and thus substantially prevents the propagation of photoresist microfissures to said material layer.
In one embodiment of the present invention, the opened hard mask formed in step (c) remains in the structure and serves as an etch stop or polishing layer for a subsequent etching or planarization process. In another embodiment, the opened hard mask is removed from the patterned structure after conducting step (d) above.
REFERENCES:
patent: 3447984 (1969-06-01), Castrucci et al.
patent: 3986697 (1976-10-01), Zielinski
patent: 4439270 (1984-03-01), Powell et al.
patent: 5882489 (1999-03-01), Bersin et al.
patent: 6090722 (2000-07-01), Armacost et al.
Jamison Paul C.
Wagner Tina
Wise Richard S.
Yan Hongwen
Capella, Esq Steven
Elms Richard
Luu Pho
LandOfFree
Hard mask process to prevent surface roughness for selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hard mask process to prevent surface roughness for selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hard mask process to prevent surface roughness for selective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2981552