Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-11
2004-09-14
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S014000, C257S355000, C257S356000
Reexamination Certificate
active
06792578
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to hard macros used in Application Specific Integrated Circuits (ASIC). More particularly, the present invention relates to eliminating antenna rule violations when routing signals to hard macro input ports, while enhancing failure analysis capability of the hard macros.
In the ASIC environment for manufacturing custom logic circuits, hard macros are integrated in a custom circuit and interconnected by metal wiring layers. A hard macro is generally a component that can be dropped into the circuit layout to perform a desired function. Examples of hard macros include processors including processor cores, memory arrays, input and output interface circuits, encoders, decoders and other types of circuit blocks.
A Reactive Ion Etch (RIE) process is generally used to establish the desired electrical connections of a layer. The RIE process may result in electrostatic charge being built up on the metal lines of each layer, which may be applied to the transistor gates of an input of the hard macro, which can permanently damage the transistor. However, the top metalization layer of the integrated circuit is ultimately connected to a diffusion area and, therefore, is not subject to having any undesirable charge accumulating on the metal segments in that layer.
Various techniques have been employed to reduce or dissipate the electrostatic charge that builds up on susceptible metal lines to avoid damaging the connected transistor. A common charge dissipation technique is to build floating gate diodes on each conductor of the input/output (I/O) port of the hard macro that connects to a gate. The diodes slowly bleed off the electrostatic charge as it accumulates on the metal line. However, as circuit densities increase, it is more difficult to find sufficient surface area for locating floating gate diodes, whose only function is to protect the gates during manufacture. Furthermore, the floating gate diodes remain as permanent circuit elements and adversely affect the performance and power dissipation of the integrated circuit.
Full chip designs can be checked before implementation into silicon for potential problem areas where charge is likely to build up during fabrication. Problem areas are detected in accordance with an antenna rule. The antenna rule compares the surface area of a metallic conductor that is connected to a gate, and the actual gate area. If the comparison exceeds a threshold value the antenna rule is violated. The metal segments that do not pass the antenna rule, risk gate failures from excessive electrostatic charge.
When violations of the antenna rule are discovered, the design can be changed to provide different routing of the metal wiring connections such that violations of the antenna rule are avoided. This process of redesigning the layout to avoid the metal/gate area threshold violation is iterative in nature and requires numerous changes to the metal wire routing and several checks for each change.
In another method, disclosed in U.S. Pat. No. 6,194,233 B1, the segments that are identified as violating the antenna rule are modified to eliminate the violation. The disclosed method involves breaking the metalization segments violating the rule for each layer of metalization. The broken segments are rejoined by a bridge formed in an adjacent layer above the break in the segment.
In addition to being inefficient, the prior art methods for fixing antenna rule violations are not always successful due to their reliance on the checker for accurately detecting problematic segments that are subject to excessive electrostatic charge buildup. Mainly, the checker used to detect antenna rule violations is prone to error causing it to falsely detect antenna rule violations or fail to detect actual ones. This is primarily the result of the checker having inaccurate gate area data for the metallic conductor of the input/output (I/O) port of the hard macro. False detections of antenna rule violations result in time-consuming work to adjust a proper layout. The failure to detect an existing antenna rule violation can cause the corresponding gates of the hard macro to be damaged and, thus, cause the hard macro to fail and require the redesign of the layout to eliminate the antenna rule violation. As a result, the reliance of the prior art methods on the checker to accurately detect antenna rule violations can result in considerable delay in the completion of an antenna rule violation-free ASIC or, an ASIC that is subject to failure due to an antenna rule violation at the I/O port of the hard macro.
Therefore, a need exists for an improved hard macro design that eliminates antenna rule violations at the I/O port of the hard macro altogether thereby avoiding the reliance on accurate antenna rule violation detection.
SUMMARY OF THE INVENTION
The present invention is directed to an improved hard macro for use in an Application Specific Integrated Circuit (ASIC) that eliminates antenna rule violations. The hard macro of the present invention includes an I/O port having a port level metallic conductor of a low level metalization layer. An I/O transistor of the hard macro includes a gate conductor that is separated from a diffusion region by a gate oxide layer. The hard macro further includes an electrical connection between the port level metallic conductor and the gate conductor that includes a first conducting section extending from the gate conductor to a top level metallic conductor at a highest level metalization layer and a second conducting section extending from the top level metallic conductor layer to the port level conductor. Antenna rule violations at the I/O port of the hard macro are eliminated due to the electrical connection between the top level metallic conductor and a diffusion region.
In addition to eliminating antenna rule violations at the I/O port of the hard macro, the electrical connection between the port level metallic conductor and the gate conductor, failure analysis of the hard macro is enhanced due to the improved accessibility of the I/O ports of the hard macro.
REFERENCES:
patent: 5654897 (1997-08-01), Tripathi et al.
patent: 6130460 (2000-10-01), Borel
patent: 6194233 (2001-02-01), Bedner et al.
patent: 6624480 (2003-09-01), Lin et al.
patent: 2002/0184601 (2002-12-01), Fitzhenry et al.
patent: 241391 (1995-02-01), None
Brown Jeffrey S.
Chafin Craig R.
LSI Logic Corporation
Thompson A. M.
Westman Champlin & Kelly
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