Handling problematic events in a data processing apparatus

Details Handling problematic events in a data processing apparatus Handling problematic events in a data processing apparatus

2006-01-24

2006-01-24

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S208000

Reexamination Certificate

active

06990569

ABSTRACT:
A data processing apparatus is provided comprising: a processor operable to execute instructions, each instruction having a micro-architectural state information associated therewith; comparator logic operable to compare the micro-architectural state information with predetermined micro-architectural state information associated with a problematic event and to issue a match signal if a match is detected; and trigger logic responsive to the match signal to provide one of a plurality of output signals, the trigger logic being programmable to determine which of the output signals is provided upon receipt of the match signal, each output signal being arranged to activate a corresponding mechanism to handle the problematic event. This advantageous arrangement alleviates problems encountered by prior art approaches by providing a programmable mechanism to identify a problematic event and to activate an appropriate mechanism to handle that problematic event. Hence, even after the hardware design of the processor has been finalised, problematic events can be identified and a mechanism activated to handle those problematic events once detected by the data processing apparatus, without requiring the faulty hardware to be modified, or the body of the software to be rewritten.

REFERENCES:
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patent: 6754852 (2004-06-01), Swoboda
patent: 2002/0184477 (2002-12-01), Swaine et al.

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