Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-09-25
2007-09-25
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
10970458
ABSTRACT:
A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few cycles before data transmission, and, when TX_ENA transitions to logic low, TX_ENA remain logic low for a few cycles. However, maintaining this timing can be difficult with back-to-back writes. Therefore, additional logic is employed within XDRAM memory controllers to insure that TX_ENA does not violate system requirements by allowing TX_ENA to remain logic high between successive writes or when the system is devoid of commands.
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patent: 2006/0123187 (2006-06-01), Bellows et al.
Bataille Pierre
International Business Machines - Corporation
Rifal D'Ann N.
Schlie Paul
Tkacs Stephen R.
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