Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-11-27
2007-11-27
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S162000, C714S006130, C714S006130
Reexamination Certificate
active
10811566
ABSTRACT:
Handling a faulting memory of a pair of mirrored memories includes initially causing a non-faulting memory of the pair of mirrored memories to service all read and write operations for the pair of mirrored memories, determining that hardware corresponding to the faulting memory of the pair of mirrored memories has been successfully replaced to provide a new memory, in response to the new memory being provided, causing data to be copied from the non-faulting memory to the new memory while data is being read to and written from the non-faulting memory, and, in response to successful copying to the new memory, causing writes to be performed to both memories of the pair of mirrored memories and selecting one of the pair of mirrored memories for read operations when one or more read operations are performed. Handling a faulting memory may also include, in response to a write being performed to the non-faulting memory while data is being copied from the non-faulting memory to the new memory, causing the write to be performed to the non-faulting memory and the new memory.
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Cartmell Jerome J.
DeCrescenzo Robert
Fan Qun
Kopylovitz Haim
McClure Steven T.
EMC Corporation
Muirhead and Saturnelli LLC
Verbrugge Kevin
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