Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt prioritizing
Patent
1997-11-13
2000-05-09
Sheikh, Ayaz R.
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt prioritizing
710128, G06F 1314
Patent
active
060617578
ABSTRACT:
An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, and to an I/O bus. Data management unit also includes interrupt routing logic which snoops interrupt packets, stores the information in registers, and generates a signal indicating whether a particular interrupt was accepted or rejected. If the interrupt logic has a higher priority interrupt pending, the current interrupt packet will be returned to the requesting device using the interrupt return transaction, and the requesting device will accept the return transaction by decoding the bus unit ID field in the packet. The interrupt will be requeued and held in a pending status until an interrupt reissue transaction is transmitted by the interrupt routing logic and received by the interrupting I/O controller. Interrupts may be generated by any I/O device connected to any of I/O controllers on the I/O bus, or by a high speed I/O device connected to processor address bus.
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Description of Intel.RTM. 8259 Controller,Intel.RTM. Peripheral Components Catalog, 1988, Intel Corp. Literature Department, 3065 Bowers Avenue, Santa Clara, California.
Arimilli Ravi Kumar
Kaiser John Michael
Maule Warren Edward
Culbertson Russell D.
England Anthony V.S.
International Business Machines - Corporation
Lefkowitz Sumati
Sheikh Ayaz R.
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