Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-12-09
2008-10-07
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C718S102000, C718S107000
Reexamination Certificate
active
07434000
ABSTRACT:
In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurality of threads in execution by the processor. Furthermore, the cache miss unit is configured to record an additional cache miss corresponding to a second thread of the plurality of threads, wherein the additional cache miss occurs in the cache prior to the cache fill completing for the cache line. The cache miss unit is configured to inhibit initiating an additional cache fill responsive to the additional cache miss.
REFERENCES:
patent: 5046068 (1991-09-01), Kubo et al.
patent: 5257215 (1993-10-01), Poon
patent: 5339266 (1994-08-01), Hinds et al.
patent: 5386375 (1995-01-01), Smith
patent: 5423016 (1995-06-01), Tsuchiya et al.
patent: 5515308 (1996-05-01), Karp et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5619439 (1997-04-01), Yu et al.
patent: 5809530 (1998-09-01), Samra et al.
patent: 5870599 (1999-02-01), Hinton et al.
patent: 5897654 (1999-04-01), Eisen et al.
patent: 5918247 (1999-06-01), Patel et al.
patent: 5933850 (1999-08-01), Kumar et al.
patent: 5954789 (1999-09-01), Yu et al.
patent: 6016542 (2000-01-01), Gottieb et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6088788 (2000-07-01), Borkenhagen et al.
patent: 6088800 (2000-07-01), Jones et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6131104 (2000-10-01), Oberman
patent: 6145054 (2000-11-01), Mehrotra et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6282554 (2001-08-01), Abdallah et al.
patent: 6341347 (2002-01-01), Joy et al.
patent: 6349319 (2002-02-01), Shankar et al.
patent: 6357016 (2002-03-01), Rodgers et al.
patent: 6381676 (2002-04-01), Aglietti et al.
patent: 6397239 (2002-05-01), Oberman et al.
patent: 6415308 (2002-07-01), Dhablania et al.
patent: 6427196 (2002-07-01), Adiletta et al.
patent: 6434699 (2002-08-01), Jones et al.
patent: 6438650 (2002-08-01), Quach et al.
patent: 6496925 (2002-12-01), Rodgers et al.
patent: 6507862 (2003-01-01), Joy et al.
patent: 6516405 (2003-02-01), Jourdan et al.
patent: 6523050 (2003-02-01), Dhablania et al.
patent: 6564328 (2003-05-01), Grochowski et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6594681 (2003-07-01), Prabhu
patent: 6625654 (2003-09-01), Wolrich et al.
patent: 6629236 (2003-09-01), Aipperspach et al.
patent: 6629237 (2003-09-01), Wolrich et al.
patent: 6658534 (2003-12-01), White et al.
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6668317 (2003-12-01), Bernstein et al.
patent: 6671827 (2003-12-01), Guilford et al.
patent: 6681345 (2004-01-01), Storino et al.
patent: 6687838 (2004-02-01), Orenstien et al.
patent: 6694347 (2004-02-01), Joy et al.
patent: 6694425 (2004-02-01), Eickemeyer
patent: 6697935 (2004-02-01), Borkenhagen et al.
patent: 6728845 (2004-04-01), Adiletta et al.
patent: 6745291 (2004-06-01), York
patent: 6748556 (2004-06-01), Storino et al.
patent: 6801997 (2004-10-01), Joy et al.
patent: 6820107 (2004-11-01), Kawai et al.
patent: 6847985 (2005-01-01), Gupta et al.
patent: 6857064 (2005-02-01), Smith et al.
patent: 6871264 (2005-03-01), Soltis, Jr.
patent: 6883107 (2005-04-01), Rodgers et al.
patent: 6889319 (2005-05-01), Rodgers et al.
patent: 6898694 (2005-05-01), Kottapalli et al.
patent: 7032076 (2006-04-01), Sprangle et al.
patent: 7134002 (2006-11-01), Shoemaker
patent: 2001/0054137 (2001-12-01), Eickemeyer et al.
patent: 2003/0046521 (2003-03-01), Shoemaker
patent: 2006/0026594 (2006-02-01), Yoshida et al.
patent: 2006/0037017 (2006-02-01), Accapadi et al.
Alverson et al., “Tera Hardware-Software Cooperation,” Tera Computer Company, 1997, (16 pages).
Alverson et al., “The Tera Computer System,” Tera Computer Company, 1990, (pp. 1-6).
Alverson et al., “Exploiting Heterogeneous Parallelism on a Multithreaded Multiprocessor,” Tera Computer Company, 1992, (pp. 188-197).
Smith et al., “The End of Architecture,” 17thAnnual Symposium on Computer Arcitecture, Seattle, Washington, May 29, 1990, (pp. 10-17).
Ungerer et al., “A Survey of Processors with Explicit Multithreading,” ACM Computing Surveys, vol. 35, No. 1, Mar. 2003, (pp. 29-63).
Office Action from U.S. Appl. No. 10/881,169 mailed Feb. 20, 2007.
Handy, “The Cache Memory Book,” 1998, Academic Press, pp. 63-64.
Office Action from U.S. Appl. No. 11/008,014, mailed Oct. 9, 2007.
Tulsen et al., “Power-sensitive multithreaded architecture,” IEEE 2000, pp. 199-206.
Uhrig et al., “Hardware-based power management for real-time applications,” Proceedings of the Second International Symposium on Parallel and Distributed Computing, IEEE 2003, 8 pages.
Tullsen, et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” ISCA 1995, pp. 533-544.
Tullsen et al., “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,” pp. 191-202, ISCA 1996.
Uhrig, et al., “Implementing Real-Time Scheduling Within A Multithreaded Java Microcontroller,” 8 pages, 2002.
Ide, et al., “A 320-MFLOPS CMOS Floating-Point Processing Unit for Superscalar Processors,” IEEE 1993, 5 pages.
Nemawarkar, et al., “Latency Tolerance: A Metric for Performance Analysis of Multithreaded Architectures,” IEEE 1997, pp. 227-232.
Baniasadi, et al., “Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors,” ACM 2001, pp. 16-21.
Gura, et al., “An End-to-End Systems Approach to Elliptic Curve Cryptography,” 16 pages, ACM 2002.
Eberle, et al., “Cryptographic Processor for Arbitrary Elliptic Curves over GF(2m),” 11 pages, IEEE 2003.
Barreh Jama I.
Shah Manish K.
Kim Matt
Krofcheck Michael C
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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