Handling cache miss in an instruction crossing a cache line...

Details Handling cache miss in an instruction crossing a cache line... Handling cache miss in an instruction crossing a cache line...

2008-07-22

2008-07-22

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S125000, C711S201000, C711S137000, C712S204000, C712S205000, C712S206000, C712S207000

Reexamination Certificate

active

07404042

ABSTRACT:
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.

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