Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-04
2002-10-01
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S525000
Reexamination Certificate
active
06458665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, in particular to a halo ion implantation method for a semiconductor device which enhances data maintenance characteristics by not allowing sources/drains of a cell transitor of a Dynamic Random Access Memory(hereinafter DRAM) to be exposed to the halo ion implantation.
2. Description of the Background Art
A halo ion implantation means implanting conductive impurity ions identical with a semiconductor substrate into the semiconductor substrate along the inside sidewalls of sources/drains of a transistor in order to prevent a short channel effect. As a result, the impurity concentration of the semiconductor substrate near the inside sidewalls of the sources/drains becomes higher than that of the semiconductor substrate in other part.
Referring to
FIGS. 1
a
through
1
c
, a conventional halo ion implantation method will be explained as follows.
A shown in
FIG. 1
a
, a gate oxide film
101
and a gate electrode
102
are formed on a first conductive type(e.g. p-type) semiconductor substrate
100
.
Next, using the gate electrode
102
as a mask, a second conductive type(e.g. n-type) impurity ions are implanted into the semiconductor substrate and heat-treated, thus forming an impurity layer
103
with a relatively shallow junction depth as compared with sources/drains which will be explained in the following process step. The second conductive type impurity ions are opposite to the first conductive type impurity ions.
Next, as shown in
FIG. 1
b
, the impurity ions of the same conductive type as that of the semiconductor substrate
100
, that is, the first conductive type(p-type) impurity ions are implanted near the sidewalls of the shallow impurity layer
103
below the gate electrode
102
, thus forming a halo ion implantation layer
104
. At this time, to implant halo ions into a lower side of the gate electrode
102
, an ion implantation is carried out at approximately 25~30 degree angle from a direction vertical to the surface of the semiconductor substrate
100
. At this time, the incidence angle leaned at 25-30 degrees is called an angle of inclination, and indicated as &thgr; in
FIG. 1
b.
Generally, in order to form the halo ion implantation layer within the gate electrode
102
, impurity ions are implanted at approximately 25-30 degree angle(that is, &thgr;=25~30°) from a vertical direction of the semiconductor substrate.
Next, as shown in
FIG. 1
c, a sidewall spacer
105
formed of an insulating film is formed on the sidewalls of the gate electrode
102
. Then, by using the sidewall spacer
105
as a mask, a second conductive type impurity ions are implanted into the semiconductor substrate
100
and heat-treated, thus forming a deep impurity layer
106
with a relatively deep junction depth as compared with the shallow impurity layer
103
. The deep impurity layer is called a source/drain of a transistor, and the shallow impurity layer is usually called a Lightly Doped Drain(LDD) in a semiconductor fabrication process.
The halo ion implantation process can be explained in detail as follows. In a conventional DRAM device fabrication process, when drawing a layout of a transistor, the layout is arranged in a vertical or horizontal direction from a flat zone of a wafer.
FIG. 2
illustrates an example of a layout of a conventional semiconductor device. Reference numeral
20
represents a wafer and reference numeral
21
is a flat zone. A region
20
a
with a high concentration of pattern(gate electrode) such as a cell array region of a DRAM device is illustrated on the left side of the dotted line, and a region
20
b
with a relatively low concentration of pattern as compared with the cell array such as a peripheral circuit region of a DRAM device is illustrated on the right side of the dotted line. Gate electrodes
22
a
are concentrated on the region
20
a
with a high concentration of pattern. Reference numeral
23
a
shown on both sides of the gate electrode
22
a
represents an impurity region
23
a
operating as a source/drain of a transistor. Additionally, gate electrode
22
b
and impurity regions
23
b
are illustrated on the region
20
b
with a relatively low concentration of pattern.
Furthermore, arrow
25
in
FIG. 2
indicates an ion implantation direction in which the sources/drains
23
a
and
23
b
are exposed to the halo ion implantation when the halo ions are implanted. Bold arrow
24
indicates a halo ion implantation direction in which the halo ions are not implanted into the sources/drains
23
a.
A detailed description thereof is as follows.
As shown in region
20
b
with a low concentration of pattern in
FIG. 2
, for a DRAM device, the pattern of the gate electrode
22
b
in the peripheral circuit region
20
b
is at once parallel to the flat zone
21
and arranged in a direction orthogonal to the flat zone
21
. Therefore, in order to carry out the halo ion implantation near all the sources/drains
23
a
of the transistor in the peripheral circuit unit, the halo ion implantation is performed in a direction d
1
that the flat zone is positioned, and in a direction d
2
that the wafer is rotated 90 degrees, 180 degrees, and 270 degrees from the flat zone
21
, respectively. Thus, the halo ion implantation is carried out in the cell region
20
a
as well in four directions d
1
, d
2
, d
3
, and d
4
. However, as the degree of integration of the DRAM device goes up, the space between the patterns(gate electrodes) becomes very narrow, so that in the case the halo ion implantation is carried out in directions d
1
and d
3
, the halo ions are almost not implanted into the sources/drains
23
a
. However, in the case that the halo ions are implanted in directions d
2
and d
4
(longitudinal directions of the gate electrode
22
a
in the cell array region), the sources/drains
23
a
are directly exposed to the halo ion implantation.
To give more, as shown in
FIG. 3
a
, in the case that the halo ions are implanted in direction
25
(that is, directions d
1
and d
3
), the gate electrode
22
a
serves as an ion implantation mask. But, in the case of direction
24
(directions d
2
and d
4
), there is no halo ion cut-off mask, and thus the halo ions are directly implanted into the sources/drains
23
a
Since
FIG. 3
a
is a vertical cross-sectional perspective view along the line IIIb—IIIb of FIG.
2
and
FIG. 3
b
is a vertical cross-sectional view along the line IIIb—IIIb of
FIG. 2
, the identical drawing symbols in
FIGS. 2
,
3
b
, and
3
b
denote the same component parts, respectively.
However, recently as the degree of integration of the DRAM increases by geometric progression recently, the size of a cell becomes smaller, resulting in a decrease in the capacity of a capacitor. For the above reason, the halo ions implanted into the sources/drains of a DRAM cell transistor cause a reverse effect of worsening the data maintenance characteristics.
That is, since a halo ion implantation layer has a high concentration of impurity, the source/drain junction forms more abrupt junction compared with the case of not applying halo ion implantation process, resulting in stronger electric field concentration at the source/drain junction where the halo ion implantation is implemented. In addition, the DRAM cell is comprised of a transistor and a capacitor, and if the electric field of a source or drain junction connected to a node electrode of the capacitor increases, the data maintenance time shortens, resulting in a decrease in the refresh characteristics. Therefore, to improve the data maintenance characteristics within the DRAM cell, the halo ion implantation process needs to be applied not to the DRAM cell transistor, but to a peripheral circuit or a core circuit alone.
Accordingly, in order to carry out the halo ion implantation into a peripheral circuit and a core circuit alone within the DRAM device and to prevent the halo ion implantation into a cell transistor, the halo ion implantation may be implemented by fo
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Mulpuri Savitri
LandOfFree
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