Grounding of package substrates

Details Grounding of package substrates Grounding of package substrates

1999-10-21

2003-05-20

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S684000, C257S687000

Reexamination Certificate

active

06566741

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor packages. More specifically, the invention relates to a method of providing grounding of a package substrate to dissipate static charge buildup during a step in the assembly of the package.
RELATED ART
An ongoing issue with manufacturing semiconductors is to maintain quality of the part, and to reduce the time spent during each manufacturing step. The issue is ever present in the assembly of semiconductor packages. During each step of a package assembly process, whether it be die attach, wirebond, encapsulation, or test, each assembly step requires time, from the beginning of the step through the end of the step.
One assembly step where there is opportunity to reduce the time is during the die encapsulation process. Die encapsulation may occur after a die is placed on a package substrate and wirebonded. Typically, the encapsulation step includes placing a substrate containing a wirebonded die, onto a platform. Then, an encapsulant, which may be an organic material for protecting the top surface of the package, is injected onto the top of the die to cover the die and the surrounding wirebonds.
More specifically, die encapsulation may include the following steps. First, a substrate that contains a die that is electrically bonded to the substrate, is placed onto a platform. The platform may be the bottom half of a mold chase. The substrate may be positioned onto the mold chase platform using alignment holes that are pre-drilled into the substrate. Once the substrate is centered on the mold chase platform, the top half of the mold chase lowers onto the substrate. The top half of the mold chase may contain a cavity within which a mold is to be formed. The cavity is located to cover the die as well as a portion of the substrate that surrounds the die. A channel within the top mold chase carries liquid mold material into the cavity. The liquid hardens to form a mold to encapsulate the die. Then, the top half of the mold chase separates from the mold chase bottom half. Ejection pins extending vertically through the bottom half of the mold chase press upward, to lift the substrate off of the mold chase bottom half. Finally, the substrate may be removed from the mold chase bottom, by human hand or by using a robot.
One problem that occurs during the encapsulation process is static charge buildup on the substrate. The substrate is typically made of an electrically insulating material, a flexible plastic or a hard ceramic material. Because of the insulative properties of the substrate, static charge builds up around the surface of the substrate because the substrate acts as a capacitor when placed in a mold chase having a different electrical potential from the package substrate. Because of the static charge buildup, it is important to make sure the static charge dissipates before the mold is separated from the substrate, and before the substrate is separated from the mold.
A solution to the charge dissipation problem is simply letting time pass. The substrate may contain a ground plane, to provide a pathway for electric charge dissipation. Letting time pass is not an realistic solution for high volume manufacturing, however, because of the impact to the throughput of the process step, as well as the inability to control the repeatability of the charge dissipation. Slight differences in electrical potential buildup with each pass of substrate through the mold chase, as well as electrical differences from substrate to substrate render it difficult to identify an appropriate time between end of encapsulation and separation from the mold.
It would be advantageous to provide a feature in the substrate to more quickly dissipate static electric charge buildup following a manufacturing operation.
SUMMARY OF THE INVENTION
According to the invention, there is a chip assembly comprising a semiconductor chip in electrical contact with a substrate, said substrate having a bottom and top surface, the semiconductor chip being in electrical contact with the substrate. The substrate contains at least one pad comprising an electrically conductive material, the pad being coupled to electrical ground, to provide a pathway for dissipating static electric charge that may occur during a manufacturing operation for the chip assembly.


REFERENCES:
patent: 5635671 (1997-06-01), Freyman et al.
patent: 5894410 (1999-04-01), Barrow
patent: 6150193 (2000-11-01), Glenn
patent: 6214645 (2001-04-01), Kim
patent: 5-55415 (1993-03-01), None

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