Graphic accelerator architecture using two graphics processing u

Details Graphic accelerator architecture using two graphics processing u Graphic accelerator architecture using two graphics processing u

1996-04-30

1999-12-14

DeCady, Albert

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

345503, G06F 1580

Patent

active

060030984

ABSTRACT:
A graphics processor is disclosed having two processing units and two dual-port RAMs for passing data between the processing units. The hardware is configured to detect whether input data is primitive information or pass-through information. If it is the former, the information is processed as a primitive. If it is the latter, the hardware determines whether one of the dual-port RAMs is available. If so, the available RAM is converted into a pass-through FIFO, and the pass-through information is stored therein. An output process operates continually to send primitive results and pass-through information from the pass-through FIFO out of the graphics processor output as the information becomes available, and ensures that the correct ordering of the information is maintained. If necessary, and if both RAMs are available, both of the dual-port RAMs in the graphics processor may be used as pass-through FIFOs at the same time.

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