Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2001-06-07
2003-02-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S763000, C438S253000
Reexamination Certificate
active
06518200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic layers within microelectronic fabrications. More particularly, the present invention relates to methods for fabricating composite microelectronic layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, so also have performance demands which are placed upon microelectronic layers, and in particular upon microelectronic dielectric layers, that are employed for fabricating microelectronic fabrications.
In particular with respect to microelectronic dielectric layers that are employed as capacitor dielectric layers within capacitors within microelectronic fabrications, there has evolved a continuing need to fabricate such microelectronic dielectric layers with enhanced compositional integrity and enhanced compositional control within limited microelectronic dielectric layer thicknesses.
While capacitor dielectric layers within capacitors within microelectronic fabrications are desirably fabricated with enhanced compositional integrity and enhanced compositional control within limited microelectronic dielectric layer thicknesses, capacitor dielectric layers within capacitors within microelectronic fabrications are nonetheless not readily fabricated with enhanced compositional integrity and enhanced compositional control within limited microelectronic dielectric thicknesses within microelectronic fabrications insofar as capacitor dielectric layers within capacitors within microelectronic fabrications are often fabricated employing methods which do not provide optimal compositional integrity and optimal compositional control.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials through which may be fabricated within microelectronic fabrications microelectronic dielectric layers with enhanced compositional integrity and enhanced compositional control.
It is towards the foregoing object that the present invention is directed.
Various microelectronic layers having desirable properties, and methods for fabrication thereof, have been disclosed in the art of microelectronic fabrication.
Included among the microelectronic layers and methods for fabrication thereof, but not limiting among the microelectronic layers and methods for fabrication thereof, are microelectronic layers and methods for fabrication thereof disclosed within: (1) Ohi et al., in U.S. Pat. No. 5,523,596 (a microelectronic capacitor dielectric layer and method for fabrication thereof comprising formed upon a first polysilicon capacitor plate a silicon oxynitride material having formed thereupon a silicon nitride material in turn having formed thereupon a silicon oxide material, such as to avoid over-oxidation of the first polysilicon capacitor plate when forming thereupon the microelectronic capacitor dielectric layer); (2) Kobayashi et al., in U.S. Pat. No. 5,616,401 (a microelectronic oxidation mask stress absorbing layer and method for fabrication thereof comprising an oxygen rich to nitrogen rich graded silicon oxynitride dielectric material formed such as to suppress a bird's beak extension when forming within a silicon semiconductor substrate an isolation region while employing a silicon nitride oxidation mask having formed thereunder the microelectronic oxidation mask stress absorbing layer); and (3) Lin et al., in U.S. Pat. No. 6,171,978 (a microelectronic capacitor dielectric layer and method for fabrication thereof comprising a continuously graded silicon oxide to silicon nitride dielectric material which provides for a variable dielectric constant within a controlled thickness within the microelectronic capacitor dielectric layer).
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications dielectric layers with enhanced compositional integrity and with enhanced compositional control.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a microelectronic layer, and a method for fabricating the microelectronic layer.
A second object of the present invention is to provide the microelectronic layer and the method for fabricating the microelectronic layer in accord with the first object of the present invention, wherein the microelectronic layer is fabricated with enhanced compositional integrity and enhanced compositional control.
A third object of the present invention is to provide the microelectronic layer and the method for fabricating the microelectronic layer in accord with the first object of the present invention and the second object of the present invention, wherein the method for fabricating the microelectronic fabrication is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a microelectronic layer and a method for fabricating the microelectronic layer.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a first layer of a first material. There is then formed upon the first layer of the first material a first transition layer of a transition material. There is then formed upon the first transition layer of the transition material a second layer of a second material. There is then formed upon the second layer of the second material a second transition layer of the transition material. Finally, there is then formed upon the second transition layer of the transition material a third layer of the first material. Within the present invention, the transition material provides a continuous transition between the first material and the second material.
The method for fabricating the microelectronic layer in accord with the present invention contemplates the microelectronic layer fabricated in accord with the method for fabricating the microelectronic layer in accord with the present invention.
There is provided by the present invention a microelectronic layer, and a method for fabricating the microelectronic layer, wherein the microelectronic layer is fabricated with enhanced compositional integrity and enhanced compositional control.
The present invention realizes the foregoing object by fabricating the microelectronic layer as a multi-layer laminate having a central layer of a second material separated from a pair of surface (or interface) layers of a first material by a pair of transition layers of a transition material, where the transition material provides a continuous transition between the first material and the second material.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations to provide a microelectronic layer in accord with the present invention. Since it is thus at least in part a series of process limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 5523596 (1996-06-01), Ohi et al.
patent: 5616401 (1997-04-01), Kobayashi et al.
patent: 6171978 (2001-01-01), Lin et al.
patent: 6300187 (2001-10-01), Smith
Taiwan Semiconductor Manufacturing Co. Ltd.
Tsai Jey
Tung & Associates
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