Global planarization using a polyimide block

Details Global planarization using a polyimide block Global planarization using a polyimide block

1994-10-25

1997-06-03

Breneman, R. Bruce

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438631, 438699, H01L 23316, H01L 2102

Patent

active

056354282

ABSTRACT:
A semiconductor device includes conductor regions 24 and 26 on a layer of the semiconductor device; a first insulator layer 28 over and between the conductor regions 24 and 26; polyimide regions 30, 32, and 34 over the first insulator layer 28 in gaps between the conductor regions 24 and 26; and a second insulator layer 38 over the first insulator layer 28 and over the polyimide regions 30, 32, and 34. A surface of the second insulator layer 38 is substantially planar.

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Wolf, Stanley, `Si Proc. for the VLSI Era`, vol. 2, Lattice Press (1990) pp. 233-235.

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