Glitch reduced compensated circuits and methods for using such

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

Reexamination Certificate

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Details

C326S030000, C326S083000, C326S086000, C327S108000, C327S170000

Reexamination Certificate

active

07550993

ABSTRACT:
Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.

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patent: 7362127 (2008-04-01), Tokuhiro et al.
patent: 2008/0211536 (2008-09-01), Nguyen et al.

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