Glitch-free dual clok read circuit

Details Glitch-free dual clok read circuit Glitch-free dual clok read circuit

1995-09-26

1997-02-25

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 365233, G11C 700, G11C 800

Patent

active

056065264

ABSTRACT:
A dual clock Read circuit for a memory array having a first latch that is set in response to a data ready signal and a second latch that is set in response to a first clock signal. Logic circuitry generates a second clock signal when the first and second latches are set. A third latch is set in response to the second clock signal for latching the data from the memory array before it is forwarded to an off-chip driver.

REFERENCES:
patent: 3939333 (1976-02-01), Keech
patent: 4607173 (1986-08-01), Knoedl, Jr.
patent: 4841174 (1989-06-01), Chung et al.
patent: 5155380 (1992-10-01), Hwang et al.
patent: 5250852 (1993-10-01), Ovens et al.

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