Glitch detection for semiconductor test system

Details Glitch detection for semiconductor test system Glitch detection for semiconductor test system

2000-04-13

2002-04-23

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C714S724000

Reexamination Certificate

active

06377065

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor devices, and more particularly, to a semiconductor test system having a glitch detection means for detecting glitches in an output signal of a semiconductor device under test to accurately evaluate the performance of the device under test.
BACKGROUND OF THE INVENTION
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test signals. The output signals are strobed or sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. Another type of test system is called an event based test system wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. The present invention is applicable to both cycle based test system and the event based test system.
An example of configuration of a traditional cycle based test system is shown in a block diagram of FIG.
1
A. In this example, a test processor
11
is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor
11
, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. A test pattern is produced by the wave formatter
14
with use of the waveform data from the pattern generator
12
and the timing data from the timing generator
13
. The test pattern is supplied to a device under test (DUT)
19
through a driver
15
in a pin electronics
20
.
A response signal from the DUT
19
resulted from the test pattern is converted to a logic signal by an analog comparator
16
in the pin electronics
20
with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data from the pattern generator
12
by a logic comparator
17
. The result of the logic comparison is stored in a failure memory
18
corresponding to the address of the DUT
19
. As noted above, the driver
15
, the analog comparator
16
as well as switches (not shown) for changing pins of the device under test, are provided in the pin electronics
20
.
An example of configuration of an event based test system is shown in a block diagram of FIG.
1
B. In an event based test system, notion of events is employed where events are any changes of the logic state in signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals or timing edges of strobe signals. The timings of the events are defined with respect to a time difference from a reference time point. Typically, such a reference time point is a timing of the previous event. Alternatively, such a reference time point is a fixed start time common to all of the events.
In an event based test system, since the timing data in a timing memory (event memory) does not need to include complicated information regarding waveform, vector, delay and etc. at each and every test cycle, the description of the timing data can be dramatically simplified. In the event based test system, as noted above, typically, the timing (event) data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Since such a time difference between the adjacent events (delta time) is small, unlike a time difference from a fixed start point (absolute time), a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
In the example of
FIG. 1B
, the event based test system includes a host computer
42
and a bus interface
43
both are connected to a system bus
44
, an internal bus
45
, an address control logic
48
, a failure memory
47
, an event memory consists of an event count memory
50
and an event vernier memory
51
, an event summing and scaling logic
52
, an event generator
24
, and a pin electronics
26
. The event based test system evaluates a semiconductor device under test (DUT)
28
connected to the pin electronics
26
.
An example of the host computer
42
is a work station having a UNIX, Window NT or Linux operating system therein. The host computer
42
functions as a user interface to enable a user to instruct the start and stop operation of the test, to load a test program and other test conditions, or to perform test result analysis in the host computer. The host computer
42
interfaces with a hardware test system through the system bus
44
and the bus interface
43
. Although not shown, the host computer
42
is preferably connected to a communication network to send or receive test information from other test systems or computer networks.
The internal bus
45
is a bus in the hardware test system and is commonly connected to most of the functional blocks such as the address control logic
48
, failure memory
47
, event summing and scaling logic
52
, and event generator
24
. An example of address control logic
48
is a tester processor which is exclusive to the hardware test system and is not accessible by a user. The address control logic
48
provides instructions to other functional blocks in the test system based on the test program and conditions from the host computer
42
. The failure memory
47
stores test results, such as failure information of the DUT
28
, in the addresses defined by the address control logic
48
. The information stored in the failure memory
47
is used in the failure analysis stage of the device under test.
The address control logic
48
provides address data to the event count memory
50
and the event vernier memory
51
as shown in FIG.
1
B. In an actual test system, a plurality of sets of event count memory and event vernier memory will be provided, each set of which corresponds to a test pin of the test system. The event count and vernier memories store the timing data for each event of the test signals and strobe signals. The event count memory
50
stores the timing data which is an integer multiple of the reference clock (integral part), and the event vernier memory
51
stores timing data which is a fraction of the reference clock (fractional part). In the preferred embodiment of the present invention, the timing data for each event is expressed by a time difference (delay time or delta time) from the previous event.
The event summing and scaling logic
52
is to produce data showing overall timing of each event based on the delta timing data from the event count memory
50
and event vernier memory
51
. Basically, such overall timing data is produced by summing the integer multiple data and the fractional data. During the process of summing the timing data, a carry over operation of the fractional data (offset to the integer data) is also conducted in the event summing and scaling logic
52
. Further during the process of producing the overall timing, timing data may be modified by a scaling factor so that the overall timing be modified accordingly.
The event generator
24
is to actually generate the events based on the overall timing data from the event summing and scaling logic
52
. The events (test signals and strobe signals) thus generated are provided to the DUT
28
through the pin electronics
26
. Basically, the pin electronics
26
is formed of a large number of components, each of which includes a driver and a comparator as well as switches to establish input and output relationships wit

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