Generic maximum aposteriori probability decoder for use in...

Details Generic maximum aposteriori probability decoder for use in... Generic maximum aposteriori probability decoder for use in...

2006-08-09

2010-02-23

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000, C714S796000, C714S794000, C714S786000, C375S341000, C375S262000

Reexamination Certificate

active

07669105

ABSTRACT:
A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

REFERENCES:
patent: 2003/0028843 (2003-02-01), Chang et al.
patent: 2003/0093741 (2003-05-01), Argon et al.
patent: 2003/0227851 (2003-12-01), Furuta et al.

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