Generation of margining voltage on-chip during testing CAM...

Details Generation of margining voltage on-chip during testing CAM... Generation of margining voltage on-chip during testing CAM...

2002-07-22

2004-03-16

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S049130, C365S185180, C365S185330

Reexamination Certificate

active

06707718

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to manufacture of flash memory devices, and more particularly, to an apparatus and method for providing margining voltages generated on-chip during testing of the CAM (content addressable memory) portion of a flash memory device.
The “Detailed Description” section is organized with the following sub-sections:
A. BIST(Built-in-Self-Test) System;
B. BIST(Built-in-Self-Test) Interface;
C. Back-End BIST(Built-in-Self-Test) State Machine;
D. On-Chip Repair of Defective Address of Core Flash Memory Cells;
E. Diagnostic Mode for Testing Functionality of BIST (Built-in-Self-Test) Back-End State Machine;
F. Address Sequencer within BIST (Built-In-Self-Test) System;
G. Pattern Generator in BIST (Built-In-Self-Test) System;
H. On-Chip Erase Pulse Counter for Efficient Erase Verify BIST (Built-In-Self-Test) Mode; and
I. Generation of Margining Voltage On-Chip During Testing CAM Portion of Flash Memory Device.
The present invention relates to sub-section “I” entitled “Generation of Margining Voltage On-Chip During Testing CAM Portion of Flash Memory Device”, with particular reference to
FIGS. 74-83
.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a flash memory cell
100
of a flash memory device includes a tunnel dielectric structure
102
typically comprised of silicon dioxide (SiO
2
) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure
102
is disposed on a semiconductor substrate or a p-well
103
. In addition, a floating gate structure
104
, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure
102
. A dielectric structure
106
, typically comprised of silicon dioxide (SiO
2
), is disposed over the floating gate structure
104
. A control gate structure
108
, comprised of a conductive material, is disposed over the dielectric structure
106
.
A drain bit line junction
110
that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area
112
of the semiconductor substrate or p-well
103
toward a left sidewall of the floating gate structure
104
in
FIG. 1. A
source bit line junction
114
that is doped with the junction dopant is formed within the active device area
112
of the semiconductor substrate or p-well
106
toward a right sidewall of the floating gate structure
104
of FIG.
1
.
During the program or erase operations of the flash memory cell
100
of
FIG. 1
, charge carriers are injected into or tunneled out of the floating gate structure
104
. Such variation of the amount of charge carriers within the floating gate structure
104
alters the threshold voltage of the flash memory cell
100
, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure
104
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure
104
, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell
100
for example, a voltage of +9 Volts is applied on the control gate structure
108
, a voltage of +5 Volts is applied on the drain bit line junction
110
, and a voltage of 0 Volts is applied on the source bit line junction
114
and on the semiconductor substrate or p-well
103
. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are injected into the floating gate structure
104
to increase the threshold voltage of the flash memory cell
100
during programming of the flash memory cell
100
.
Alternatively, during erasing of the flash memory cell
100
, a voltage of −9.5 Volts is applied on the control gate structure
108
, the drain bit line is floated at junction
110
, and a voltage of +4.5 Volts is applied on the source bit line junction
114
and on the semiconductor substrate or p-well
103
for example. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are pulled out of the floating gate structure
104
to decrease the threshold voltage of the flash memory cell
100
during erasing of the flash memory cell
100
. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of −9.5 Volts is applied on the control gate structure
108
and a voltage of +9 Volts is applied on the semiconductor substrate or p-well
103
with the drain and source bit line junctions
110
and
114
floating. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are pulled out of the floating gate structure
104
to the substrate or p-well
103
to decrease the threshold voltage of the flash memory cell
100
during erasing of the flash memory cell
100
.
FIG. 2
illustrates a circuit diagram representation of the flash memory cell
100
of
FIG. 1
including a control gate terminal
150
coupled to the control gate structure
108
, a drain terminal
152
coupled to the drain bit line junction
110
, a source terminal
154
coupled to the source bit line junction
114
, and a substrate or p-well terminal
156
coupled to the substrate or p-well
103
.
FIG. 3
illustrates an electrically erasable and programmable memory device
200
comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to
FIG. 3
, the array of flash memory cells
200
includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell
100
of
FIGS. 1 and 2
. The array of flash memory cells
200
of
FIG. 3
is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to
FIG. 3
, in the array of flash memory cells
200
comprising an electrically erasable and programmable memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In
FIG. 3
, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line
202
, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line
204
.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In
FIG. 3
, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line
206
, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line
208
. Further referring to
FIG. 3
, the source terminal of all flash memory cells of the array
200
are coupled together to a source voltage V
SS
, and the substrate or p-well terminal of all flash memory cells of the array
200
are coupled together to a substrate voltage V
SUB
.
Referring to
FIG. 4
, a flash memory device comprised of an array of flash memory cells as illustrated in
FIG. 3
for example is fabricated on a semiconductor die of a semiconductor wafer
220
. A plurality of semiconductor dies are manufactured on the semiconductor wafer
220
. Each square area on the semiconductor wafer
220
of
FIG. 4
represents one semiconductor die. More numerous semiconductor dies are typically fabricated on a semiconductor wafer than shown in
FIG. 4
for clarity of illustratio

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