Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-29
2007-05-29
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000, C703S014000
Reexamination Certificate
active
11238822
ABSTRACT:
A test pattern sequence to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected and an initialization test pattern v1which establishes an initial value for activating the fault at the location of a fault is determined by an implication operation. A propagation test pattern v2which causes a stuck-at fault to be propagated to a following gate is determined by another implication operation. A sequence formed by v1and v2is registered with a test pattern list and the described operations are repeated until there remains no unprocessed fault in the fault list.
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Ishida Masahiro
Yamaguchi Takahiro
Advantest Corporation
Britt Cynthia
Gallagher & Lathrop
Lathrop, Esq. David N.
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