Generating responses to patterns stimulating an electronic...

Details Generating responses to patterns stimulating an electronic... Generating responses to patterns stimulating an electronic...

2011-07-19

2011-07-19

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S032000, C714S724000, C714S726000, C714S727000, C714S729000, C703S003000, C703S004000, C703S013000, C703S014000, C703S019000, C703S021000, C703S022000, C703S023000

Reexamination Certificate

active

07984354

ABSTRACT:
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

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