Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-07-12
2011-07-12
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07979765
ABSTRACT:
Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device100generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation device100includes a selection unit101for selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unit103for calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unit105for assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.
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International Search Report for PCT/JP2007/068505 dated Dec. 25, 2007.
Date Hiroshi
Kajihara Seiji
Minamoto Yoshihiro
Miyase Kohei
Wen Xiaoqing
Gaffin Jeffrey A
Japan Science & Technology Agency
Kyushu Institute of Technology
Nguyen Steve
Rankin , Hill & Clark LLP
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